Abstract: An apparatus that inspects wire breaking of a semiconductor integrated circuit includes a voltage applying device (12), a light pulse source (14), a scanning device (16), an electromagnetic wave detection device (18), and a wire breaking detection device (20). The voltage applying device (12) maintains a semiconductor integrated circuit in a state where a predetermined voltage is being applied thereto. The light pulse source (14) generates an ultrashort light pulse (2). The scanning device (16) two-dimensionally scans and irradiates the two-dimensional circuit of the semiconductor integrated circuit by using the ultrashort light pulse (2). The electromagnetic wave detection device (18) detects an electromagnetic wave (3) radiated from a position irradiated with the ultrashort light pulse on the semiconductor integrated circuit. The wire breaking detection device (20) detects wire breaking of the irradiated position based on presence and absence or intensity of the electromagnetic wave.

Abstract: Improved methods for performing burn-in of electronic components, such as integrated circuits (ICs) with on-board thermal sense circuits, are used to obtain a higher bin split. According to one embodiment, a thermal set-point is loaded into each IC. While the ICs are maintained at a constant elevated temperature, the burn-in system checks each IC to determine whether the set-point has been exceeded. If so, it characterizes the IC by that set-point; if not, it decrements the set-point and checks again. The method continues until all ICs have been characterized to a specific set-point. As a result of the method, a junction temperature is obtained for each IC. In addition, a real-time estimate of the burn-in time for each IC is obtained, so that burn-in time can be adjusted to maximize burn-in throughput. Apparatus for implementing improved IC burn-in is also described.

Abstract: A method of manufacturing a probe test head for testing of semiconductor integrated circuits includes: defining shapes of a plurality of probes as one or more masks; a step for fabricating the plurality of probes using the mask; and disposing the plurality of probes through corresponding holes in a first die and a second die. The step for fabricating the plurality of probes may include one of photo-etching and photo-defined electroforming.

Abstract: The invention involves a semi-conductor component testing system, a process for semi-conductor components, as well as an assembly, more particularly a wafer with several semi-conductor components to be tested, whereby each semi-conductor component is allocated an individual identifying label, more particularly an identification-number, in order to perform the test—done individually for each semi-conductor component—on the respective semi-conductor component.

Abstract: A probe needle apparatus having a conductive central core with alternating layers of dielectric and conductive materials is provided. The apparatus includes the conductive central core, a first layer of dielectric material applied to maintain electrical access to the conductive central core while providing continuous isolation of the conductive central core elsewhere, and a conductive driven guard layer applied around the first layer of dielectric material in electrical isolation from the conductive central core. The conductive driven guard layer is applied on the first layer of dielectric material with a mask on an end of the conductive central core to prevent the conductive driven guard layer from touching the conductive central core.

Abstract: The present invention provides an apparatus and a method for used in a board inspection capable of an inspection of defect in a circuit board with high resolution over a wide range. The method is used for manufacturing a sensor probe comprising layers which include an electrode layer, a lead wire layer and a bridge layer (41). These layers are laminated on a base (30) in the form of a flat plate composed of silicon. The electrode layer is comprised of a set of sensor electrodes (40). The lead wire layer is comprised of a set of lead wires (50) for transferring a signal externally. The bridge layer couples between the electrode layer and the lead wire layer. The lead wire layer is formed by means of depositing aluminum in accordance with a first mask pattern. The bridge layer is formed by means of growing each of bridge wires (41) in the direction perpendicular to the base. The bridge wires extend in the direction perpendicular to the base and are connected to respective lead wires of the lead layer.

Abstract: An apparatus and method for the real-time, in-line testing of semiconductor wafers during the manufacturing process. In one embodiment the apparatus includes a probe assembly within a semiconductor wafer processing line. As each wafer passes adjacent the probe assembly, a source of modulated light, within the probe assembly, having a predetermined wavelength and frequency of modulation, impinges upon the wafer. A sensor in the probe assembly measures the surface photovoltage induced by the modulated light. A computer then uses the induced surface photovoltage to determine various electrical characteristics of the wafer.

Abstract: The invention provides a unitary spring contact probe comprising a resilient spring section, a plunger section extending from a distal end of the resilient spring section for contacting a semiconductor device under test and a stopper projecting from the plunger section substantially transversely to an axial direction of the plunger section. There is also provided an apparatus for testing a semiconductor comprising a plurality of said unitary spring contact probes, one or more insulative guiding holders for mounting the spring contact probes, and a retainer mechanism coupled to the stoppers of the spring contact probes for securing the spring contact probes to the insulative guiding holders.

Abstract: A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of the IC's pads. The flex cable provides relatively high bandwidth signal paths linking the tester to probes accessing others of the IC's pads.

Abstract: The present invention provides an apparatus and method for inspecting a circuit board at a high speed. A PDP driver module 100 as an object to be inspected has an onboard PDP driving LSI 110. A plurality of circuit wirings 111 are connected to terminals of the LSI. An inspection apparatus 1 generates an LSI drive signal and sends it to input terminals 113 of the LSI 110. A sensor 2 is positioned opposedly to the circuit wirings 111 in a non-contact manner. The sensor 2 detects voltage values in circuit wirings 111 caused by driving the LSI 110, and the detected signals are analyzed by the inspection apparatus 1.

Abstract: An test block includes a box-like body and four rails extending from side edges of the body. During thermal testing, the test block is mounted between a test head and a test socket such that the rails provide a thermal path between the test block body and contact pads formed on the test socket. In this manner the rails emulate the thermal path formed by the metal leads extending from a conventional Quad Flat Pack Integrated Circuit (QFP IC), thereby reliably duplicating the actual thermal path of the QFP IC. The test block is mounted on the test system and its temperature is measured before and after testing QFP IC devices. Confirming that the test block is within test temperature specifications before and after the QFP-IC test procedure provides a highly reliable verification that the QFP-IC's actual test temperature is within the test temperature specifications.

Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.

Abstract: A system, method, and apparatus are arranged to provide small-signal compensation in a switching regulator that includes an inductor. A zero adjustment circuit is included in the system to introduce at least one zero in the closed-loop transfer function associated with the regulator. The zero adjustment circuit is responsive to a measurement signal, which is associated with one or more measured parameters associated with the inductor. By changing the location of at least one zero in response to the measurement signal it is possible to dynamically change the compensation based on variations in the inductance of the inductor. The zero adjustment circuit may be provided as a portion of the controller block of the regulator, or as a separate feedback circuit. The zero adjustment circuit can be implemented digitally as a portion of a DSP block, or as an analog function as may be desired in a particular system.

Abstract: An electronic apparatus includes a specific circuit component having a circuit constant included in a function circuit serving a specific circuit function, and a measurement terminal for measuring the circuit constant. The circuit constant has a value in accordance with a specification. The electronic apparatus can avoid a misidentification during an identification procedure of the specification.

Abstract: An interface device provides an interface between testing equipment and an integrated circuit to be tested. The interface device includes a body member. A number of elongate contact members are mounted on the body member. Each contact member includes a contact end, adapted to contact a bond pad of the integrated circuit to be tested, and a body portion. The interface device also includes a guide member mounted on the body member. The guide member includes a substantially planar member having a number of apertures therein, and the contact end of each elongate member extending through a respective aperture in the guide member.

Abstract: In previously known methods for testing internal signals of an integrated circuit, additional output pins were required which, in general, were linked to additional measuring pads within the integrated circuit. In the new method, the circuit functions are tested by using the output pins at which the output signal is present during normal operation of the integrated circuit. By means of a simple, external connection, with which a defined voltage value is set at the signal output, the integrated circuit is switched by means of an integrated control unit into a test mode in which it applies selected signals, which are to be tested, at the signal output. There is no need for additional internal measuring pads or additional output pins.

Abstract: An integrated circuit can be tested externally at its normal signal output pin(s) without requiring additional testing output pins or test measuring pads. The integrated circuit includes a circuit unit that generates a normal output signal provided to the signal output pin in a normal operating mode and generates a test signal in a testing mode, a switching element that selectively does or does not connect the test signal from the circuit unit to the signal output pin, and a control unit that controls the switching element with a control signal responsive to the potential level present at the signal output pin. When the circuit is to be tested, a defined voltage is applied to the signal output pin by a voltage divider formed of resistors between a supply voltage and a reference voltage. This causes the control unit to close the switching element.

Abstract: The present invention provides an apparatus and a method for used in a board inspection capable of an inspection of defect in a circuit board with high resolution over a wide range. The method is used for manufacturing a sensor probe comprising layers which include an electrode layer, a lead wire layer and a bridge layer (41). These layers are laminated on a base (30) in the form of a flat plate composed of silicon. The electrode layer is comprised of a set of sensor electrodes (40). The lead wire layer is comprised of a set of lead wires (50) for transferring a signal externally. The bridge layer couples between the electrode layer and the lead wire layer. The lead wire layer is formed by means of depositing aluminum in accordance with a first mask pattern. The bridge layer is formed by means of growing each of bridge wires (41) in the direction perpendicular to the base. The bridge wires extend in the direction perpendicular to the base and are connected to respective lead wires of the lead layer.

Abstract: A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

Abstract: An apparatus and method for the real-time, in-line testing of semiconductor wafers during the manufacturing process. In one embodiment the apparatus includes a probe assembly within a semiconductor wafer processing line. As each wafer passes adjacent the probe assembly, a source of modulated light, within the probe assembly, having a predetermined wavelength and frequency of modulation, impinges upon the wafer. A sensor in the probe assembly measures the surface photovoltage induced by the modulated light. A computer then uses the induced surface photovoltage to determine various electrical characteristics of the wafer.