Abstract: A method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

Abstract: A large array probe/contact having spring characteristics for relieving stress in the contact caused, for example, by temperature change is fabricated using a unique combination of semiconductor fabrication operations. The contacts in the array have a “U” shaped resilient portion, are fixed at one end to a substrate and have an accessible low electrical noise contact tip. The contacts are encapsulated on the substrate in an elastomer to provide additional stress relief resilience, support and protection from damage during handling.

Abstract: In one embodiment, a contactor (200) is provided. The contactor (200) comprises a device side (210), a test circuit board side (155), and a thickness (110). The device side (210) is in communication with at least three electrical contact points (140, 141, 142) of the device (170). The test circuit board side (155) includes a fourth electrical contact point (193) in electrical communication with the circuit board (150). The contactor (200) also includes a first electrical pathway (220) between the first electrical contact point (140) and the second electrical contact point (142). The first electrical pathway (220) bypasses the circuit board (150). The contactor (200) further includes a second electrical pathway (270) between the third electrical contact point (142) and the fourth electrical contact point (193).

Abstract: An electrical circuit testing device is provided, comprising a case, a digital voltage level testing circuit with a display means, a switch to initiate measurement using the device, a non-shorting switching means for selecting pre-determined electrical wiring configurations to be tested in an outlet, a terminal block, a five-pole electrical plug mounted on the case surface and a set of adapters that can be used for various multiple-pronged electrical outlet configurations for voltages from 100–600 VAC from 50–100 Hz.

Abstract: A programmable fuse state determination system and method provide a fuse current through a programmed fuse which produces a voltage that varies with the fuse's resistance. The voltage is compared with a threshold voltage to indicate whether the fuse is blown or intact. The invention employs ‘normal’ and ‘test’ modes, in which the relationship between the fuse's resistance and the threshold voltage differ, such that a higher fuse resistance is required for the fuse to be determined blown in the ‘test’ mode than in the ‘normal’ mode.

Abstract: A probe card assemblage for simultaneously testing one or more integrated circuit chips including an interposer having on one surface a plurality of protruding contact elements for electrically contacting one or more chips of a wafer positioned atop a layer of compliant material, and arrayed in a pattern corresponding to a chip pads, a series of conductive vias through the electrically insulating interposer which connect the chip contact elements with an arrangement of leads terminating in a universal arrangement of connectors on the second surface, and a probe card with connectors mating to those on the interposer. The connectors on the interposer is secured are secured to those on the probe card, thereby providing a vertical probe assemblage which makes use of ultrasonic energy to minimize scrub or over travel. The universal probe card is specific to a tester configuration and common to a family of circuits to be tested.

Abstract: A method and system to achieve shallow junctions using Electromagnetic Induction Heating (EMIH) that can be preceded or followed by a low-temperature Rapid Thermal Annealing (RTA) process. The methods and systems can use, for example, RF or microwave frequencies to induce electromagnetic fields that can induce currents to flow within the silicon wafer, thus causing ohmic collisions between electrons and the lattice structure that heat the wafer volumetrically rather than through the surface. Such EMIH heating can activate the dopant material. Defects in the silicon structure can be repaired by combining the EMIH annealing with a low-temperature (approximately 500–800 degrees Celsius) RTA that causes minimal diffusion, thus minimizing the difference between the as-implanted junction depth and the post-annealing junction depth when compared to annealing methods that only use traditional RTA.

Abstract: Disclosed herein is a semiconductor device loading apparatus for test handlers. The semiconductor device loading apparatus includes a body. The apparatus body includes a plurality of pickup cylinders provided with a plurality of vacuum adsorbers for vacuum-sucking and transferring semiconductor devices to be tested, a space adjusting plate for adjusting the pitches of the vacuum adsorbers, and an elevation guiding means for guiding the lifting and lowering of the space adjusting plate. A guide block fixing plate is formed to be separate from the body for guiding the semiconductor devices to be accurately positioned in the pockets of a test tray, respectively.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.

Abstract: A contactless sheet resistance measurement apparatus and method for measuring the sheet resistance of a surface p-n junction and its leakage current is disclosed. The apparatus comprises an alternating light source optically coupled with a transparent and conducting electrode brought close to the junction, a second electrode placed outside of the illumination area, and a third grounded electrode surrounding the first and second electrodes. For measurements of junction capacitance, a calibration wafer with known sheet resistance is used to provide reference photovoltage signals. Using the measurement of the junction photovoltage (JPV) signals from the illuminated area and outside this area for calibration and test wafers at different light modulation frequencies, p-n junction sheet resistance and conductance (leakage current density) are determined.

Abstract: A method for detecting a power load of a power supply module, includes: receiving a pulse width modulation (PWM) signal generated by the power supply module, wherein the PWM signal is utilized for controlling a driving voltage outputted from the power supply module; detecting a duty cycle of the PWM signal; and determining the power load of the power supply module according to the duty cycle.

Abstract: A semiconductor tester for testing a semiconductor device by generating pulses of different repetition periods to a DUT having ports of different periods (frequencies) without using plural timing memories holding timing sets. The semiconductor tester required to generate a timing edge pulse of a period M different from a test period N of the semiconductor tester comprises period converting means capable of generating a timing edge pulse of the period M different from the period N of the test rate without using timing set that the semiconductor tester has.

Abstract: A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

Abstract: Several embodiments of massively parallel interface structures are disclosed, which may be used in a wide variety of permanent or temporary applications, such as for interconnecting integrated circuits (ICs) to test and burn-in equipment, for interconnecting modules within electronic devices, for interconnecting computers and other peripheral devices within a network, or for interconnecting other electronic circuitry. Preferred embodiments of the massively parallel interface structures provide massively parallel integrated circuit test assemblies. The massively parallel interface structures preferably use one or more substrates to establish connections between one or more integrated circuits on a semiconductor wafer, and one or more test modules. One or more layers on the intermediate substrates preferably include MEMS and/or thin-film fabricated spring probes.

Abstract: A time division multiplexed optical voltage measuring system includes an optical voltage sensing system module including, (i) a plurality of optical sensors where each sensor is responsive to an input interrogation light wave, and (ii) one or more optical outputs affected by sensed electric field thereat. The optical voltage sensing system module includes an optical circuit arrangement having (i) an input for receiving a module specific pulsed light wave derived from a primary pulsed light wave from a remote light source, and (ii) arranged such that each of the plurality of optical sensors receives an interrogation pulsed light wave. The optical circuit arrangement of the optical voltage sensing system module further includes at least one optical wave combiner for combining like-kind of outputs from all of the plurality of optical sensors. The optical circuit is arranged such that the pulsed light waves from the outputs of different optical sensors arrive at the optical wave combiner at differing times.

Abstract: A method for sensing the state of an electrophoretic display includes the steps of applying an electrical signal to a display element, measuring an electrical response for the display element, and deducing the state of the display element from the measured electrical response. Also, the parameters of the display materials are determined using the encapsulated electrophoretic display media as a sensor, either alone or in conjunction with other sensors.

Abstract: A prober which tests an object to be tested under temperature control is provided. This prober includes a stage base, Z stage, X-Y stage having a frame structure, substrate fixing mechanism arranged on the X-Y stage, a probe card arranged to oppose the substrate fixing mechanism, and a probing stage fixed on the Z stage and arranged in the frame structure of the X-Y stage such that its axis coincides with an extension line vertically extending from the probe center of the probe card. The probing stage includes a probing elevating mechanism, and a temperature controller to heat and cool the object to be tested. The probing stage supports the substrate of the object to be tested from the bottom surface, and controls the temperature of the object to be tested.

Abstract: A waveform display position adjusting apparatus is provided for more conveniently and rapidly adjusting a position at which a waveform is displayed on a waveform display device. The apparatus is configured to adjust a position at which a waveform represented by a waveform input signal is displayed on the display device having a two-dimensional display area. The apparatus comprises a mapping unit for mapping a two-dimensional waveform value space for a waveform input value derived from the waveform input signal to the two-dimensional display area of the display device, and a mapping adjusting unit coupled to the mapping unit for adjusting the mapping. The mapping adjusting unit comprises a continuous mapping adjusting section coupled to the mapping unit for continuous adjusting of the mapping.

Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate, shaped openings in the substrate, or shaped portions of the substrate. The spring segments are configured to flex to exert spring forces on the component contacts, and to compensate for variations in the size or planarity of the component contacts. The interconnect can be configured to test wafer sized components, or to test die sized components. A test method includes the steps of providing the interconnect with the interconnect contacts, and electrically engaging the component contacts under a biasing force from the spring segments. A wafer level test system includes the interconnect mounted to a testing apparatus such as a wafer probe handler.

Abstract: An IC-chip testing system includes multiple digital state machines, and a master controller which controls the operation of those digital state machines by a particular method. In this method, the master controller first generates a command chain in which multiple commands for one particular digital state machine are concatenated together in a series. Thereafter, the master controller sends a single payload data packet embedded in a layered TCP/IP/network format, to that digital state machine. This single payload data packet includes the entire command chain. By concatenating many commands together in the command chain, the adverse effect of TCP/IP/network headers on the efficiency of transmission is overcome. In one particular transmission, efficiency is increased from 7.1% for sending a single command, to 89.4% for sending the entire command chain.