Abstract: An electronic calibration component for calibrating a tester device is described. The calibration component has a signal input, to which a tester channel to be calibrated can be connected, and a phase difference circuit. The phase difference circuit can be connected to the signal input and can be connected to a reference clock signal. As a result, a phase difference information item is determined between a cyclic signal applied to the signal input and the reference clock signal. The electronic calibration component also has an output device in order to output the phase difference information item. The latter is received by a tester device that can be connected to the calibration component via tester channels. The tester device has a delay device that is connected to the tester channel in order to delay signals to be transmitted on the tester channel on the basis of the phase difference information item.

Abstract: A method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

Abstract: A semiconductor device test apparatus according to the present invention includes a circuit board 103 and a film 105. A plurality of electrodes 103c are formed at the circuit board 103 at positions that face opposite a plurality of electrodes 201a at a device to be measured 201, whereas bumps 105b are formed at the surface of the film 105 located toward the device to be measured 201, at positions that face opposite the plurality of electrodes 201a at the device to be measured 201 and electrodes 105c are formed at the surface of the film 105 located toward the circuit board 103 at positions that face opposite the plurality of electrodes 103c at the circuit board 103. The bumps 105b formed at one surface of the film 105 and the electrodes 105c formed at another surface of the film 105 are electrically connected with each other via through holes 105d to support semiconductor devices having electrodes provided at a fine pitch and to improve durability.

Abstract: A leakage current of a dielectric overlaying a semiconductor wafer can be determining by moving a conductive probe into contact with the dielectric and applying an electrical stimulus, in the form of a fixed amplitude, fixed frequency AC voltage superimposed on a DC voltage which is swept from a starting voltage towards an ending voltage, between the probe tip and the semiconductor wafer. Conductance values associated with the dielectric and the semiconductor wafer can be determined from phase angles between the AC voltage and an AC current resulting from the applied AC voltage during the sweep of the DC voltage. The leakage current of the dielectric can then be determined from the thus determined conductance values.

Abstract: To be able to test a plurality of identical semiconductor circuit devices in a particularly rapid yet reliable manner, a test method includes carrying out the tests in parallel and substantially simultaneously on the plurality of semiconductor circuit devices and driver lines—used in the process—of a test device to the semiconductor circuit devices simultaneously and jointly for all the semiconductor circuit devices. In such a case, test results are read from a plurality of input/output channels in compressed form. Furthermore, as an alternative or in addition thereto, the semiconductor circuit devices to be tested are disposed and connected up in at least one stack.

Abstract: A method and apparatus are disclosed for enabling reconfiguration of a test system. The test system includes an adapter assembly (106) and a tester electronics assembly (108). The adapter assembly (106) includes two probe plates (200, 202), which hold a probe field (116). The two probe plates (200, 202) include a plurality of holes (208) extending through each probe plate (116). Each hole (208) includes a flange area (206) for accommodating deflection of the probes (204), inserted in the holes (208) extending through the probe plates (200, 202). The flange area (206) and the use of flexible probes (204) facilitate a deflection and an offset (210) of the probes (204) in the probe plates (200, 202). A tester assembly (300) includes a plurality of wear pads (308) on the topside of a printed circuit board (302). The wear pads (308) positioned to engage the bottom end of the probes (204).

Abstract: A testing system for automatic testing of circuit boards (1) in a circuit board manufacturing line. The testing system comprises a set (I) of test modules (4) comprising a testing apparatus. Each test module comprises a horizontal module conveyor (5) for conveying a circuit board (1) into and out of the test module. The test modules are arranged in a superposed relation with respect to each other. The set (I) contains test modules differing from each other so that the testing operations performed by these test modules are different from each other. A feed device (6) has been fitted to receive circuit boards from the first line conveyor (3) and to feed them into the test modules (4).

Abstract: Testing system for automatic testing of circuit boards (1) in a circuit board manufacturing line. The system comprises a set of test modules (4) comprising a testing apparatus, each test module comprising a horizontal module conveyor (5) for moving a circuit board (1) into and out of the test module, which test modules are arranged into a superposed relation with respect to each other. A feed device (6) has been fitted to receive and arrange a number of circuit boards from a first line conveyor (3) into a superposed relation with respect to each other so that the circuit boards (1) lie at a distance from each other corresponding to the distance between the module conveyors (5) and to feed the circuit boards substantially simultaneously into the test modules (4).

Abstract: A temperature-controlled system and method for supporting a wafer or packaged integrated circuit (IC) under test are described. The system includes a thermal platform having a top surface assembly on which the wafer or IC can be mounted. A thermal plate is located under and in thermal communication with the top surface assembly. The thermal plate is made of a porous thermally conductive material. A temperature-controlled fluid such as air enters and propagates radially through the porous material of the thermal plate. The temperature of the wafer or IC is controlled by controlling the temperature of the air passing through the thermal plate. The plate can be made of a sintered metal such as copper or a reticulated foam or a carbon or graphite foam.

Abstract: This invention pertains to a high density interconnection test connector intended especially for verification of integrated circuits, including a plate supporting a multiplicity of conductive pins one of the ends of which forms a contact zone with the electronic circuit to be tested and the other end forms a contact zone with a connecting plate that has a connection means with the test equipment, with the conductive pins presenting a form that is capable of ensuring flexibility and including a longitudinal component, characterized in that the pins present a succession of at least three arc-shaped sections (4, 5, 6) in alternating directions extended on both sides by rectilinear segments that are mobile according to one degree of freedom in axial translation, with the pins being inserted in the front plates.

Abstract: An inspection apparatus is provided capable of adequately positioning an inspection chip to a conductive pattern as an inspection object. For connecting an electrode pad 1b of an inspection chip 1 with a lead 2a of a package 2, bump electrodes 3 and 4 are first provided at the inspection chip and at the package, respectively. Then, an anisotropic conductor 5 is provided to cover between the bump electrodes 3 and 4, and a conductor film 6 is provided on the anisotropic conductor 5 to extend between the bump electrodes 3 and 4. The anisotropic conductor 5 is thermo-compression bonded to provide an electrical connection between the conductor film 6 and the bump electrodes 3 and 4. This structure may provide a desirable surface of the inspection chip 1 having a sufficiently reduced thickness.

Abstract: A device for verifying frequency of a clock signal generated from a clock signal generator includes a reference signal generator, a frequency divider and a comparative detector. A reference clock signal and a reset signal are provided by the reference signal generator. The frequency divider in communication with the reference signal generator and the clock signal generator receives and frequency-divides the clock signal into a bi-level divided clock signal in response to the reset signal. Then the comparative detector in communication with the frequency divider and the reference signal generator detects a level of the bi-level divided clock signal in response to the reset signal and the reference clock signal, and verifies frequency of the clock signal according to a period deviation range Te when the bi-level divided clock signal is detected to be a first level from the first to the (p?q)th detected points but a second level at the (p+1)th detected point.

Abstract: To measure the resistance from one end of a conductor (4) to the other or between conductors, for the purpose of testing them, by establishing an electric current in the conductor, without any mechanical contact therewith, this method includes providing opposite and proximate to the conductor (4)a plate (2) that has a plurality of conductive zones (8, 10) capable of being individually taken to any adjustable electric potentials, applying a beam of particles (7) to a first point (C) of the conductor (4) to extract electrons from it, and injecting electrons at a second point (B) of the conductor (4).

Abstract: An inspection technique for enabling an inspection on a wafer at an early stage during a wafer process. A wafer in a process is irradiated with an electron beam a plurality of times at predetermined intervals under a condition that a junction is backward biased, and secondary electron signals are monitored, so as to evaluate relax time characteristic of a backward bias potential in a p-n junction. Since the potential in the p-n junction decreases according to the intensity of a backward bias current in intermittent time, a backward bias current can be specified from an intensity signal interrelated with the number of secondary electron signals, that is, a potential contrast image on the basis of image information.

Abstract: A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: The present invention provides an impedance measuring device for a printed wiring board. The device include an appropriate probe unit to locate measuring points on the printed wiring board. The probe unit has a probe with contact styli to be contacted with the measurement points. The probe is moved to make an arrangement of the contact styli matching the pattern of the measurement points.

Abstract: A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to be input into the semiconductor and/or response signals generated by the semiconductor device in response to the test signals.

Abstract: A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low-profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned-in and tested in a more efficient and cost-effective manner than prior known BGA or FBGA semiconductor packages. A high-density, low-profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: A probe includes at least one core and at least one sense coil associated with the core. The ends of the core are arranged in a contact-free, spaced relationship between opposed surfaces of adjacent lamination teeth of a stator. Air gaps are maintained between the ends of the probe core and the opposed surfaces. The total of the two air gaps is constant. The probe is supported on a carriage arrangement and moved along the teeth. Variations in leakage flux produced with the stator energized with an energization winding to produce a flux which is a few percent of is normal energization level, are monitored.