Patents Examined by Jerome Jackson
  • Fin formation in fin field effect transistors
    Patent number: 9379218
    Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 28, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz, Yunpeng Yin
  • Nonvolatile memory device
    Patent number: 9379320
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 28, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Shingu, Akira Takashima, Koichi Muraoka
  • High power electronic component with multiple leadframes
    Patent number: 9373566
    Abstract: In an embodiment an electronic component includes a semiconductor die having a first surface, the first surface including a first current electrode and a control electrode. The electronic component further includes a die pad having a first surface, a plurality of leads and a gull-wing shaped conductive element coupled to a first lead of the plurality of leads. The first current electrode is mounted on the die pad and the gull-wing shaped conductive element is coupled between the control electrode and the first lead.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: June 21, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Teck Sim Lee
  • Luminous element
    Patent number: 9373745
    Abstract: A light emitting device according to the embodiment includes a first conductive semiconductor layer; an active layer over the first conductive semiconductor layer; a second conductive semiconductor layer over the active layer; a bonding layer over the second conductive semiconductor layer; a schottky diode layer over the bonding layer; an insulating layer for partially exposing the bonding layer, the schottky diode layer, and the first conductive semiconductor layer; a first electrode layer electrically connected to both of the first conductive semiconductor layer and the schottky diode layer; and a second electrode layer electrically connected to the bonding layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 21, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: June O Song
  • Thin film transistor and method of manufacturing the same, and electronic apparatus
    Patent number: 9368738
    Abstract: A thin film transistor includes: an organic semiconductor layer which is formed from a metal-containing material containing at least one of a metallic element and a semi-metallic element capable of reacting with an etching gas; a source electrode and a drain electrode spaced apart from each other; and an organic conductive layer which is inserted between the organic semiconductor layer and the source and drain electrodes in the regions where the organic semiconductor layer overlaps with the source and drain electrodes and which is formed from a non-metal-containing material not containing at least one of a metallic element and a semi-metallic element capable of reacting with the etching gas.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: June 14, 2016
    Assignee: Sony Corporation
    Inventor: Mao Katsuhara
  • Thin film transistor and manufacturing method thereof, array substrate and display device
    Patent number: 9368637
    Abstract: A thin film transistor (TFT) and manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor comprises a substrate; an active layer formed on the substrate; a first conductive contact layer and a second conductive contact layer formed on the active layer; an etch-stop layer formed over the first contact layer and the second contact layer; and a source connected with the first contact layer, a drain connected with the second contact layer and a gate arranged between the source and the drain formed over the etch-stop layer. The TFT has a simple structure and better performance.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: June 14, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Zhang, Chunsheng Jiang, Dongfang Wang, Haijing Chen, Fengjuan Liu
  • Method and apparatus for creating a W-mesa street
    Patent number: 9368674
    Abstract: A method for fabricating an epitaxial structure includes providing a wafer comprising one or more epitaxial layers. The wafer is divided into dice where the area between the dice are called streets. Each street has a slot formed on either side of the street. The slots penetrate through the epitaxial layer but not the substrate leaving a portion of the epitaxial layer intact between the slots creating a “W” shaped cross section. A protective layer is then formed on the wafer. A laser may be used to singulate the wafer in to individual dice. The laser divides each street between the slots. The barrier walls of the epitaxial layers protect the individual dice from debris created by laser separation.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 14, 2016
    Assignee: Koninklijke Philips N.V.
    Inventors: Songnan Wu, Boris Kharas
  • Method for manufacturing a micromechanical component
    Patent number: 9365417
    Abstract: A method for manufacturing a micromechanical component includes the following sequential steps: a first material layer including a first joining partner being applied to a first wafer; a second material layer including a second joining partner being applied to a second wafer; a micromechanical structure being created in the first wafer by gas phase etching with the aid of a gaseous etching medium which is applied to the first joining partner; the first and second wafers being joined in such a way that they are in contact at least in some areas; and the first and second joining partners being heated to be integrally joined to form a connecting layer, a eutectic joining material being formed in the connecting layer from the first joining partner and the second joining partner.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 14, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Thomas Mayer, Heribert Weber, Jens Frey
  • Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array
    Patent number: 9362264
    Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 7, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Masaki Tamaru, Kazuyuki Nakanishi, Hidetoshi Nishimura
  • Article and panel comprising semiconductor chips, casting mold and methods of producing the same
    Patent number: 9362144
    Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: June 7, 2016
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Thorsten Meyer, Markus Brunnbauer
  • Method for fabricating pipe gate nonvolatile memory device
    Patent number: 9362301
    Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: June 7, 2016
    Assignee: SK Hynix Inc.
    Inventors: Ki-Hong Lee, Kwon Hong, Dae-Gyu Shin
  • Semiconductor device having a base, a cavity, a diaphragm, and a substrate
    Patent number: 9363617
    Abstract: A semiconductor device has a semiconductor element having a base, a cavity having a polygonal horizontal cross-section penetrating vertically through the base, a diaphragm arranged on the base to cover the cavity, and a substrate formed with a die bonding pad. A lower surface of the semiconductor element is adhered on the die bonding pad with a die bonding resin. The die bonding pad is formed so as not to contact a lower end of a valley section formed by an intersection of wall surfaces of an inner peripheral surface of the cavity of the semiconductor element.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 7, 2016
    Assignee: OMRON Corporation
    Inventors: Kazuyuki Ono, Tomofumi Maekawa
  • Semiconductor device with recess, epitaxial source/drain region and diffuson
    Patent number: 9356146
    Abstract: A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 31, 2016
    Assignee: SONY CORPORATION
    Inventor: Takuji Matsumoto
  • OLEDs and other electronic devices using desiccants
    Patent number: 9356258
    Abstract: Electronic devices that use desiccants for protection from moisture. The electronic devices comprise a substrate and an organic element disposed over the top surface of the substrate. The substrate has one or more voids which may store desiccants. The voids may penetrate partially or completely through the thickness of the substrate. An environmental barrier is disposed over the organic element and the voids. Also provided are methods for making electronic devices that use desiccants.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: May 31, 2016
    Assignee: Universal Display Corporation
    Inventors: Ruiqing Ma, Jeffrey A. Silvernail
  • Planar device on fin-based transistor architecture
    Patent number: 9356023
    Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.
    Type: Grant
    Filed: March 30, 2013
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Peter J. Vandervoorn, Chia-Hong Jan
  • Non-planar semiconductor device with aspect ratio trapping
    Patent number: 9349594
    Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping is provided, including a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The oxide layer has an aspect ratio that is selected to substantially eliminate defects at the interface between the oxide layer and the fins. The semiconductor device may also include a semiconductor layer between the bulk substrate and oxide layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Semiconductor device having capacitors
    Patent number: 9349724
    Abstract: A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: May 24, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon-bae Kim, Yong-chul Oh, Kuk-han Yoon, Kyu-pil Lee, Jong-ryul Jun, Chang-hyun Cho, Gyo-young Jin
  • Higher stability read head utilizing a partial milling process
    Patent number: 9349397
    Abstract: In one embodiment, a method for forming a magnetoresistive read head includes forming a fixed layer having a first ferromagnetic material that has a fixed direction of magnetization above a lower shield layer, forming a free layer having a second ferromagnetic material positioned above the fixed layer, the free layer having a non-fixed direction of magnetization, forming a first mask above the free layer, the first mask having a predetermined width based on a track width of a magnetic medium, etching the free layer down to the fixed layer using the first mask as a guide, wherein substantially none of the fixed layer is etched, and wherein the fixed layer extends beyond both sides of the free layer in a cross-track direction, and forming magnetic domain control films on both sides of the free layer in the cross-track direction, the magnetic domain control films including a soft magnetic material.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 24, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Masashi Hattori, Norihiro Okawa, Kouichi Nishioka, Kouji Okazaki
  • Methods and apparatus for ESD structures
    Patent number: 9343555
    Abstract: Methods and apparatus are disclosed for ESD protection circuits. An ESD protection circuit may comprise a first region of an n type material, a second region of a p type material adjacent to the first region, a third region of an n type material within the second region and separated from the first region, and a fourth region of a p type material within the third region. There may be multiple parts within the first region and the second region, made of different n type or p type materials. An ESD protection circuit may further comprise a fifth region of a p type material, contained within the first region.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Yu Kuo, Chi-Kuang Chen
  • Vertical power component
    Patent number: 9343557
    Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 17, 2016
    Assignees: STMICROELECTRONICS (TOURS) SAS, UNIVERSITE FRANCOIS RABELAIS
    Inventors: Samuel Menard, Gaël Gautier