Patents Examined by Jerome Jackson
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Patent number: 9520434Abstract: An image pickup module includes: an image pickup chip including a main surface on which a light-receiving portion of an image pickup device and a plurality of electrodes connected to the light-receiving portion are formed; and a wiring board including flying leads bonded to the respective plurality of electrodes.Type: GrantFiled: October 2, 2014Date of Patent: December 13, 2016Assignee: OLYMPUS CORPORATIONInventor: Masashi Yamada
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Patent number: 9515256Abstract: Phase transition devices may include a functional layer made of functional material that can undergo a change in conductance in response to an external stimulus such as an electric or magnetic or optical field, or heat. The functional material transitions between a conducting state and a non-conducting state, upon application of the external stimulus. A capacitive device may include a functional layer between a top electrode and a bottom electrode, and a dielectric layer between the functional layer and the top electrode. A three terminal phase transition switch may include a functional layer, for example a conductive oxide channel, deposited between a source and a drain, and a gate dielectric layer and a gate electrode deposited on the functional layer. An array of phase transition switches and/or capacitive devices may be formed on a substrate, which may be made of inexpensive flexible material.Type: GrantFiled: August 3, 2015Date of Patent: December 6, 2016Assignee: PRESIDENTS AND FELLOWS OF HARVARD COLLEGEInventors: Shriram Ramanathan, Dmitry Ruzmetov, Venkatesh Narayanamurti, Changhyun Ko
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Patent number: 9515089Abstract: Fabricating a semiconductor device includes providing a substrate, wherein the substrate is comprised of a base layer, a doped silicon layer on top of the base layer, and an undoped silicon layer on top of the doped silicon layer; forming a hard mask layer on top of the substrate; forming at least one mandrel on top of the hard mask layer; forming a spacer layer on top of exposed portions of the hard mask layer and the at least one mandrel; etching portions of the spacer layer; removing the at least one mandrel; etching regions of the hard mask layer and the undoped silicon layer not protected by remaining portions of the spacer layer to form at least one fin; and removing the remaining portions of the spacer layer.Type: GrantFiled: May 14, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin
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Patent number: 9508850Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.Type: GrantFiled: February 1, 2016Date of Patent: November 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Zhenyu Hu, Richard J. Carter, Andy Wei, Qi Zhang, Sruthi Muralidharan, Amy L. Child
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Patent number: 9502551Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.Type: GrantFiled: August 18, 2015Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
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Patent number: 9496218Abstract: An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.Type: GrantFiled: June 17, 2013Date of Patent: November 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Sun Lee, Kun-Sang Park, Byung-Lyul Park, Seong-min Son, Gil-heyun Choi
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Patent number: 9496252Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.Type: GrantFiled: February 12, 2016Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Akram A. Salman
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Patent number: 9490421Abstract: A method and system provide a magnetic junction usable in a magnetic device and which resides on a substrate. The magnetic junction includes a reference layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer, the nonmagnetic spacer layer and the reference layer form nonzero angle(s) with the substrate. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.Type: GrantFiled: January 28, 2013Date of Patent: November 8, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dmytro Apalkov, Alexey Vasilyevitch Khvalkovskiy, Vladimir Nikitin, Steven M. Watts
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Patent number: 9490250Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further includes a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.Type: GrantFiled: January 27, 2015Date of Patent: November 8, 2016Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Franz Hirler, Joachim Weyers, Uwe Wahl
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Patent number: 9484511Abstract: A light emitting device includes a light emitting element, a terminal substrate and a fixing member. The light emitting element is a semiconductor laminate having a first semiconductor layer, a light emitting layer, and a second semiconductor layer that are laminated in that order, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The terminal substrate includes a pair of terminals connected to the first electrode and the second electrode, and an insulator layer that fixes the terminals. At least a part of the outer edges of the terminal substrate is disposed more to a center of the light emitting device than the outer edges of the semiconductor laminate. The fixing member fixes the light emitting element and the terminal substrate.Type: GrantFiled: May 12, 2014Date of Patent: November 1, 2016Assignee: NICHIA CORPORATIONInventors: Ryoma Suenaga, Hiroto Tamaki
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Patent number: 9484505Abstract: An LED structure is applied to a backlight source to set a white light of a backlight module at a standard D65 position of the CIE1931 chromaticity coordinates and used together with a display module. A red phosphor for emitting a red light, a yellow phosphor for emitting a yellow light, and a blue light LED chip are provided. The mixing ratio of the red phosphor to the yellow phosphor is controlled within a range of (2.33?1):1, so that the original LED white light falls within a region enclosed by ccy?1.8*ccx?0.12, ccy?1.8*ccx?0.336, ccy?0.33 and ccy?0.15 of the CIE1931 coordinates. Since the red phosphor does not absorb or convert yellow light, the brightness loss of the yellow light that excites the yellow phosphor is minimized. A color filter may be installed to achieve better NTSC effect and luminous efficacy.Type: GrantFiled: August 29, 2014Date of Patent: November 1, 2016Assignee: Unity Opto Technology Co., Ltd.Inventors: Chih-Chao Chang, Hung-Li Yeh, Po-Hsiang Chung, Chun-Che Lin, Ru-Shi Liu
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Patent number: 9484205Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.Type: GrantFiled: December 30, 2014Date of Patent: November 1, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn
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Patent number: 9478597Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.Type: GrantFiled: September 10, 2009Date of Patent: October 25, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
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Patent number: 9472522Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.Type: GrantFiled: November 7, 2013Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Jie Chen
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Patent number: 9472624Abstract: A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.Type: GrantFiled: March 15, 2013Date of Patent: October 18, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-youn Kim, Joo-sung Kim, Moon-seung Yang
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Patent number: 9466751Abstract: A novel photodetecting device having field confined by mesas is provided. The device is an avalanche photodiode (APD) of indium aluminum arsenide (InAlAs). The device has epitaxial layers with a multiplication layer at bottom as a cathode. Hence, the strongest electric field is confined inside the bottom of the device to avoid surface breakdown. Double mesa is used to confine the electric field of the multiplication layer. Furthermore, a composite multiplication layer with supper thin thickness and wide bandgap is used to reduce the tunneling dark current. Hence, the thickness of equivalent multiplication layer can be reduced to enhance sensitivity.Type: GrantFiled: March 4, 2016Date of Patent: October 11, 2016Assignee: NATIONAL CENTRAL UNIVERSITYInventor: Jin-Wei Shi
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Patent number: 9455183Abstract: A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.Type: GrantFiled: March 6, 2013Date of Patent: September 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Chen-Hua Yu, Shin-Puu Jeng, Chih-Hang Tung, Cheng-Chang Wei
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Patent number: 9455307Abstract: There is provided a method of forming an active matrix electro-optical device, the method comprising providing a backplane comprising: a backplane substrate; a semiconductor particle formed separately from the backplane substrate and then fixed upon the backplane substrate at a predetermined position; the semiconductor particle planarized to remove portions of the semiconductor particle and to expose at a cross-section of the semiconductor particle a planar surface; and a controllable gated electronic component on or directly beneath the planar surface, the controllable gated electronic component configured to control one or more pixels of the electro-optical device. The method also comprises providing an optical portion comprising one or more pixel regions, the optical portion electrically connected to the backplane such that at least one of the pixel regions of the optical portion is electrically connected to the controllable gated electronic component.Type: GrantFiled: October 9, 2015Date of Patent: September 27, 2016Assignee: DIFTEK LASERS, INC.Inventor: Douglas R. Dykaar
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Patent number: 9450005Abstract: An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section.Type: GrantFiled: March 27, 2014Date of Patent: September 20, 2016Assignee: Sony CorporationInventors: Takeshi Yanagita, Suguru Saito, Kaoru Koike
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Patent number: 9443972Abstract: A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench.Type: GrantFiled: November 30, 2011Date of Patent: September 13, 2016Assignee: Infineon Technologies Austria AGInventor: Oliver Blank