Abstract: In a semiconductor device such as a thin film transistor a semiconductor region is formed and an insulating film is formed on the semiconductor region to have a contact hole extending to the semiconductor region. An electrically conductive metal layer is formed of aluminum to fill the contact hole. An electrically conductive protection layer is formed on the metal layer to prevent oxidation of the metal layer during manufacturing of the semiconductor device. Material of the protection layer is more difficult to be oxidized than aluminum. A transparent electrode is formed on the protection layer such that the electrode is electrically connected to the semiconductor region. The protection layer may be formed of titanium or a laminate layer of a titanium layer and a titanium nitride layer.

Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.

Abstract: The present invention is An electrical interconnection on a substrate and a method for forming an electrical interconnection on a substrate. The electrical interconnection in the present invention comprises a first metal layer, a first diffusion barrier layer on the first metal layer, a second metal layer on the first diffusion barrier layer, an organometallic layer on the second metal layer, and an electrical interconnect layer on the organometallic layer. The first diffusion barrier layer prevents diffusion of the first metal layer and the second metal layer therethrough. The organometallic layer is preferably formed by contacting the second metal layer with an organic material to form a organometallic layer. The organometallic layer chemically and physically protects the second metal layer, particularly by preventing the oxidation thereof.

Abstract: A semiconductor package which includes a package substrate and a semiconductor chip located on the package substrate have coefficients of thermal expansion which differs by a large margin. The semiconductor chip has beveled edges and an epoxy is provided which reduce stresses on the semiconductor chip when the package is being heated.

Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.

Abstract: A semiconductor device is formed with interconnections having reduced electric resistance. The semiconductor device comprises an upper wiring formed on an insulating film with a barrier metal therebetween, a conductive plug formed in a plugging space of the insulating film and electrically connected to the upper wiring at an opening of the plugging space, and a sidewall formed on a side surface of the upper wiring, the bottom of the sidewall covering the opening of the plugging space not covered by the upper wiring.

Abstract: A semiconductor device is provided with a wiring body including an insulating supporting substrate, and signal lines, power lines and ground lines printed on first and second surfaces of the insulating supporting substrate. The wiring body is mounted on a semiconductor chip, inside pads of the lines of the wiring body are connected with bonding pads on the semiconductor chip through first metal lines, and outside pads of the lines are connected with leads of a lead frame. Since the wiring body has a structure in which the lines are supported by the insulating supporting substrate, refined and various line patterns can be formed by using the wiring body, and an impedance matching function can also be attained. Thus, the invention provides a semiconductor device which can exhibit high noise resistance for a high frequency signal and a high operation speed and a wiring body to be disposed in a high frequency circuit.

Abstract: An improved bonding system is provided in which a metal heat spreader is bonded to semiconductor chip. A two adhesive system is used in which a first adhesive demonstrates high bond strength with a second adhesive exhibits high thermal conductivity.

Abstract: Packaging of high resolution linear solid state image sensors can result in a significant cost savings over conventional packaging processes, while adding several features. Cost reduction is accomplished by drastically reducing the cover glass size, eliminating the need for rounded corners as well as need for an epoxy ring on the cover glass, and integrating a wire bond light shield into the IC package. Additional cost savings are realized by eliminating the thermal cure cycle presently required to attach the cover glass, a process which can take several hours to completed. The invention replaces the conventional IC package with a two piece assembly. The bottom piece is a low profile plastic or ceramic IC package and the top piece is an inexpensive molded piece which serves as a cap with an integrated light shield aperture and cover glass holder.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: The present invention relates to semiconductor devices packaged using overcasting. The overcast devices of the present invention incorporate encapsulative materials, such as ultraviolet-curing material, which are cast in open stencils at approximately ambient pressure (and potentially at approximately ambient temperature) over electronic components mechanically and electrically connected to the substrate. The overcast semiconductor devices of the present invention may incorporate new encapsulative materials, including UV-cured materials and longer shelf life materials, poorly suited for the pressures and temperatures of injection molding. The overcast devices also allow the incorporation of substrate materials which are not feasible for use with a higher pressure, higher temperature forming process.

Abstract: A method for selective conductivity etching of a silicon carbide (SiC) semiconductor includes forming a p-type SiC layer on a substrate layer, forming an n-type SiC layer on the p-type SiC layer, and photoelectrochemically etching selected portions of the n-type SiC layer by applying a bias voltage to the n-type SiC layer in a hydrofluoric acid (HF) solution while exposing the layer to a pattern of UV light. The bias potential is selected so that the n-type SiC layer will photo-corrode and the p-type SiC layer will be inert and act as an etch stop. The light pattern exposure of the n-type SiC layer may be done by applying a photolithographic mask to the layer, by projecting a collimated light beam through a patterned mask, or by scanning with a focused micrometer-sized laser beam on the semiconductor surface.

Abstract: A method for preventing bonding pads from peeling caused by plug process comprises the following steps. First, a substrate is prepared, and then a first conductor is formed on the substrate. Next, a dielectric layer is formed on the first conductor. After that, a big contact window and a plurality of small contact windows are formed on the dielectric layer, wherein the plurality of small contact windows are located around the big window, and the sizes of the big contact window and small contact windows are over 3 .mu.m. Subsequently, a metal plug layer is formed on the dielectric layer, big contact window and small contact windows. Thereafter, the metal plug layer is etched back to form metal spacers on the sidewalls of the big contact window and small contact windows. Finally, a second conductor is formed on the dielectric layer, big contact window, small contact windows and metal spacers.

Abstract: A multi-layered conductive device is constituted of a plurality of conductive elements disposed in at least two layers, and an insulating film disposed between the respective conductive elements. The multi-layered conductive device may be manufactured by forming a single conductive element, adhering an insulating film to at least one surface of the conductive element, cutting the conductive element to form at least two conductive strips, laminating at least two layers of conducting elements to from a single assembly and fixing the assembly with a resin.

Abstract: An integrated circuit package which contains an integrated circuit. The internal integrated circuit is coupled to external lands located on a first outer surface of the package by a plurality of vias. The vias extend through the package from the first outer surface to an opposite second outer surface. The package has a plurality of devices such as capacitors that are mounted to the second outer surface. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.

Abstract: A highly heat conductive heat sink comprising diamond particles yet eliminating heat distortion problems caused by the difference in thermal expansion with a semiconductor, and a manufacturing method thereof. Melting of an alloy (C), which comprises a metal (A) of at least one metal selected from the group consisting of Cu, Ag, Au, Al, Mg, and Zn; and a metal (B) of at least one metal selected from the group consisting of the groups 4a and 5a of the Periodic Table and chromium, around diamond particles forms on the surface thereof a metal carbide (B'), which enables the strong bonding between the diamond particles and the metal (A) and thus produces a highly heat conductive heat sink having a much higher thermal conductivity than the metal (A). This structure is attainable by either an infiltration method or sintering method.

Abstract: The present invention relates to a laminated chip bead element demonstrating noise absorption characteristics over a broad range in a high frequency range of GHz or higher. An insulating body is constituted of a material achieved by mixing ferrite powder and an insulating resin. At least one signal conductor is embedded in the insulating body. It is desirable that the insulating body includes a plurality of composite members.

Abstract: After forming the first contact embedded in the first insulating film, a wire is formed on the first contact and a side wall made of an insulative substance is formed on a side surface of the wire. The second insulating film made of a substance different from the side wall is layered in a region including the wire, and a via hole for embedding the second contact is provided in the second insulating film under such an etching condition that the side wall is harder to etch, and therefore an end portion of the wire is not etched and an exposed area of an internal wall of the via hole can be reduced. It is possible to suppress deterioration gap-filling characteristics due to gas discharge from the second insulating film and achieve a contact of good shape. Thus, this structure avoids deterioration in imbedding characteristics that is caused by a deviation of alignment when the wire is interposed between a stacked via consisting of the first and second contacts.

Abstract: A high-reliability COG-type liquid crystal display device is produced with a high production yield without using a thermo-compression bonding process thereby preventing the connection of a liquid crystal driver IC from encountering a failure which would otherwise occur due to a high temperature in the thermo-compression bonding process. The liquid crystal display device comprises a pair of substrates (13, 14) facing each other via a liquid crystal, at least a liquid crystal driver IC (7) mounted on one substrate (13) by means of direct connection to the one substrate (13), and a plurality of semiconductor input terminals (21) formed on the substrate (13) so that signals are applied to the IC (7) via the semiconductor input terminals (21). The semiconductor input terminals (21) of the liquid crystal panel (8) are connected to semiconductor driving output terminals (6) of a portable telephone device or the like via an elastic connector (12).

Abstract: An integrated circuit combination includes a second piggy-back small integrated circuit chip mounted on the carrier of a first integrated circuit chip. The combination can be mounted on a board without requiring board space for interconnecting the first and second chips. The lid of the first chip is cut away so that the second chip can be mounted to the first without increasing the height of the combination over the height of the first chip. The two chips preferably comprise an FPGA and a PROM for programming the FPGA. The combination increases security as well as reducing board space because it is difficult to read a bitstream being transmitted from the PROM to the FPGA when the PROM is directly mounted on the FPGA.