Abstract: A semiconductor device includes a buffer region having buffers and disposed along a side of a semiconductor chip; a pad region having pads corresponding to the buffers and disposed outside the buffer region on the semiconductor chip; signal lines connecting the buffers to corresponding pads; and power supply lines and ground lines connected to extra pads, either of the power supply lines or the ground lines being partially superimposed on part of and separated from the signal lines by insulating layers.

Abstract: A pad block is provided with a pad, an output buffer circuit and an internal circuit. The region between the internal circuit and the output buffer circuit serves as an element arrangement forbidden region. In this region, the internal circuit and the output buffer circuit are connected to each other by, for example, a polysilicon layer. The internal circuit is connected to a circuit formed in an internal region of a chip by using at least two wiring layers passing the element arrangement forbidden region. By laying out the wiring connecting the internal circuit within the pad block to the circuit in the internal region of the chip in the element arrangement forbidden region provided within the pad block, it is possible to reduce a space necessary for wiring and thereby to realize a highly integrated device.

Abstract: For electron beam wafer or mask processing, a registration mark is capacitively coupled to the top surface of an overlying resist layer on a substrate to form a voltage potential on the surface of the resist layer directly over the registration mark. The registration mark is directly connected to an electrical lead that produces an AC voltage on the registration mark, which is capacitively induced on the surface of the resist layer. Alternatively, the registration mark itself is capacitively coupled to a conductive plate placed on the bottom surface of the semiconductor substrate. An AC voltage is then applied to the conductive plate that induces a charge on the registration mark, which then capacitively induces a charge on the surface of the layer of resist. An electron beam scanning across the surface of the resist layer generates secondary electrons. The secondary electrons have a low energy and are affected by the voltage potential created at the surface of the resist layer.

Abstract: A circuit assembly comprising a substrate, a first set of contacts, a second set of contacts, and a third set of contacts. Also, a plurality of electrically conductive lines located on the substrate providing electrical connection between the first set of contacts, the second set of contacts, and the third set of contacts, wherein the plurality of electrically conductive lines are configured such that data can be transferred between the first set of contacts, the second set of contacts and the third set of contacts. A first die is electrically connected to the first set of contacts, and a molding compound surrounds the substrate, wherein the molding compound is formed such that the second set of contacts is exposed allowing electrical connection of the second die to the second set of contacts.

Abstract: To provide a check pattern whereby whether via-hole openings are made correctly or not can be examined without needing high precision positioning of the via-holes, a check pattern of the invention comprises: a check wiring (3) configured on a semiconductor substrate (2), an insulation film (4) formed on the semiconductor substrate (2) to cover the check wiring; and a pair of via-holes (6) each configured at each end of the check wiring (3), said each (6) positioned slightly shifted inversely with each other from a center line in a width direction of the check wiring (3), and a bottom of said each (6) being positioned to traverse both the check wiring (3) and the insulation film (4).

Abstract: A monolithic silicon mass flow control structure is made by etching process to form a valve structure and a channel in a silicon chip, laser or electric discharge process to form a flow inlet and a flow outlet in a glass chip, and anode connection process to combine the silicon chip and the glass chip. At least a flow sensing element and a micro valve control element are disposed above the channel and the valve structure respectively for flow sensing and control purposes. A semi-complete product is sealed on a base board, wherein an output signal from the flow sensing element is compared with a pre-set value in an externally connected control circuit, which will change heating condition so as to control flow of the valve structure.

Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Abstract: A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide.

Abstract: A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder/flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction.

Abstract: Integrated circuit regions are formed on an integrated circuit wafer. The integrated circuit wafer includes scribe regions located between the integrated circuit regions, the scribe regions include test pads that are electrically connected to the test circuits of integrated circuit regions via conductive lines. Test functions are provided to the test circuits in the integrated circuit regions via the test pads to determine the operability of the integrated circuit regions. The integrated circuit regions are separated from the plurality of scribe regions and the plurality of test pads located therein. Separating the integrated circuit regions from the scribe regions and the test pads, thereby may allow a reduction in the number of pads in the integrated circuits and a corresponding decrease in the size of respective integrated circuit packages.

Abstract: A circuit board assembly includes an integrated circuit package. A first substrate has first and second surfaces. Each surface of the first substrate has a plurality of terminal pads. An integrated circuit device has first and second faces. The first face has a plurality of electrical interconnections to the terminal pads in the first surface of the first substrate. A heatspreader plate has a plurality of legs. For example, the heatspreader may be shaped like a table with four legs. The heatspreader may be formed of copper. The second face of the integrated circuit device is connected to the heatspreader plate by a first thermal interface material. Each of the plurality of legs is connected to the first surface of the first substrate by a second thermal interface material. The first and second thermal interface materials may both be, for example, a conductive silver-filled epoxy. The heatspreader provides an open package that is easily cleaned and drained.

Abstract: Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Abstract: An embodiment of an inventive semiconductor device comprises an unpackaged semiconductor wafer section having a major surface with a plurality of bond pads thereon. A plurality of conductors each comprise a lead member and at least a portion formed within a matrix. The conductors are attached to the major surface of the wafer section. An electrical connection electrically couples each of the bond pads with at least one of the lead members. Sealing material is then formed to contact at least the bond pads and the lead members.

Abstract: A semiconductor package includes a lead frame having a die pad for a semiconductor chip to be mounted thereon. The die pad is surrounded by a plurality of leads for electrically connecting the semiconductor chip and has one opening formed to decrease the attaching area between the semiconductor chip and the die pad so as to prevent the occurrence of declamination. A base pad is provided to be coupled to the die pad in such a manner that the base pad is positioned underneath or above the die pad and has a bottom surface or a top surface to be exposed to the extension of a resin encapsulant for enclosing the semiconductor chip and a portion of the lead frame, allowing the base pad to serve as a heat dissipater for transferring heat of the semiconductor package to the ambient.

Abstract: A leadless IC or other electronic circuit package socket is provided which is of simple construction providing low profile mounting of an IC package on a circuit board. The socket comprises a relative thin socket carrier having a plurality of resilient conductive columns extending between the top and bottom surfaces of the carrier and having alignment elements which are cooperative with elements on a circuit board on which the carrier is mounted to position the carrier on the circuit board such that the conductive columns are in registration and electrical contact with corresponding ones of contacts on the circuit board. An IC package or other circuit package has contacts on the bottom surface thereof in a pattern corresponding to the pattern of the resilient conductive columns of the socket carrier, and also has alignment elements cooperative with elements on the socket carrier to provide alignment of the package contacts and the conductive columns when the package is mounted on the socket carrier.

Abstract: Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Polysilicon 12 is formed on the side walls of the trench 5, and the metallic contaminants within the element forming region are collected in this polysilicon 12.

Abstract: A thermally-enhanced flip chip integrated circuit (IC) package has a package substrate to which an IC die is bonded. A thermally-conductive heatspreader, having planar dimensions larger than the IC die, is thermally bonded at or near its center to an upper surface of the IC die. A plurality of cooling extensions are formed that protrude from a lower surface (the surface closest to the package substrate) of the heatspreader so as to create passageways through which cooling air may flow. In one embodiment, the cooling extensions are parallel fins that protrude transversely from the lower surface of the heatspreader, thereby forming U-shaped channels. In another embodiment, the cooling extensions are an array of fin pins that protrude transversely from the lower surface of the heatspreader.

Abstract: A power bus grid architecture for an integrated circuit including a plurality of main bars assembled along the perimeter of the grid and a plurality of bus bars assembled within the perimeter of the grid. The bus bars are each composed of a plurality of segments with each segment having a substantially constant width. Each segment on certain bus bars has a different width from the next adjacent segment. The width of a particular segment is determined by the distance of the segment from the nearest main power bar. Because the current flow through the segments nearest to the main power bar tends to be greater than the current flow through the segments further from the main power bar, the segments nearest to the main power bar can be made much wider than the segments furthest from the main power bar without significant deleterious effects to the circuit from voltage drops or electromigration.

Abstract: A two-step masking process is disclosed for forming a ball limiting metallurgy (BLM) pad structure for a solder joint interconnection used between a support substrate and a semiconductor chip. A solder non-wettable layer and a solder wettable layer are deposited on the surface of a support substrate or semiconductor chip which are to be connected. A phased transition layer is deposited between the wettable and non-wettable layers. A thin photo-resist mask defines an area of the solder wettable and phased layers which are etched to form a raised, wettable frustum cone portion. A second mask is deposited on the surface of the support substrate or semiconductor chip, and has an opening concentrically positioned about the frustum cone. Solder is deposited in the opening and covers the frustum cone and the area about its periphery. When solidified, the solder, acting as a mask, is used to sub-etch the underlying solder non-wettable layer thereby defining the BLM pad.

Abstract: The present invention provides a semiconductor package comprising: an electrically conductive base plate having a first surface comprising first, second and third regions; a semiconductor chip provided on the first region of the electrically conductive base plate and the semiconductor chip having at least a first electrode and at least a second electrode; an insulation layer provided on the third region of the electrically conductive base plate; and an electrically conductive thin film pattern laminated on the insulation layer and the electrically conductive thin film pattern being electrically connected to the first electrode of the semiconductor chip, so that the electrically conductive thin film pattern and the first electrode have a first variable potential, wherein the second electrode is connected directly to the second region of the electrically conductive base plate so that the second electrode and the electrically conductive base plate has a second fixed potential which is different from the first va