Abstract: A semiconductor photodetector includes a SOI substrate; a p-i-n photodiode provided on the SOI substrate, the p-i-n photodiode having an i-type semiconductor region; an insulator film provided on the i-type semiconductor region; and a depleting electrode provided on the insulator film. The semiconductor photodetector exhibits its function well with or without a power source for applying a voltage to the depleting electrode for depleting it. When the power source for depletion is used, the function of the device is realized at a voltage for depletion applied from the power source for depletion lower than a biasing voltage applied from a biasing power source.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate, a stiffener, a heat spreader, and an optional heat sink. The chip includes multiple I/O pads arranged upon an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The stiffener, a rigid member able to retain its shape during C4 heating, may be attached to the upper surface of the substrate prior to the C4 process, helping the substrate maintain its planarity during and after the C4 process. The stiffener has an opening dimensioned to receive the chip and exposing the first set of bonding pads. Following the C4 process, a first space between the underside surface of the chip and the upper surface of the substrate is filled with an underfill material.

Abstract: A novel method for coating a semiconductor die/leadframe assembly prior to encapsulation. The method of the invention comprises coating the exposed surfaces of the die and the inner lead fingers in a die/leadframe assembly with an adhesion promoting material, typically a polyimide. A solution of the adhesion promoting material is dispensed from a spray nozzle to coat the die and the inner lead fingers. Preferably, all exposed surfaces of the die, the inner lead fingers and the bond wires are coated prior to encapsulation. The invention also provides an improved semiconductor package that includes a semiconductor die/leadframe assembly and a layer of adhesion promoting material coating the exposed surfaces of the die and the inner lead fingers. The die/leadframe assembly is encapsulated in a molded plastic package.

Abstract: A microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts.

Abstract: There is provided a semiconductor device including a substrate, a first insulating film formed on the substrate, a first electrically conductive layer formed on the first insulating film, a dielectric layer formed on the first electrically conductive layer, the dielectric layer being formed with a first through-hole, a second electrically conductive layer formed on the dielectric layer, the second electrically conductive layer being formed with a second through-hole in alignment with the first through-hole, a second insulating film covering the first and second electrically conductive layers therewith, and a first wiring layer formed on the second insulating film, a first contact hole being formed through the second insulating film, and the dielectric layer and the second electrically conductive layer both in the first and second through-holes, the first wiring layer making electrical contact with the first electrically conductive layer through the first contact hole.

Abstract: Integrated circuitry and a method of forming a contact landing pad are described. The method includes, in one embodiment, providing a substrate having a plurality of components which are disposed in spaced relation to one another; forming a silicon plug spanning between two adjacent components; forming a refractory metal layer over the silicon plug and at least one of the components; reacting the silicon plug and the refractory metal layer to form a silicide layer on the silicon plug; and after forming the silicide layer removing unreacted refractory metal layer material from the substrate.

Abstract: A connectorized substrate and method of connectorizing a substrate is provided, including a substrate having conductive traces mounted thereon and solder paste connected to the conductive traces and conductive spheres mounted to the solder paste. The connectorized substrate of the present invention may be used to provide for components to be added to a motherboard such as a resistor network by mounting resistors to the conductive traces of the substrate such as thick-film ceramic resistors.

Abstract: A light emitting element (1) and a light receiving element (2) are oppositely fixed through a space by an opaque-material package (3) to allow transmission and reception of light therebetween. The light emitting element and the light receiving element have leads which are outwardly extended from a bottom surface (A) of the package (3) and inserted into and soldered to through-holes of a substrate. A movement-preventing bend portion (11g, 21g) having at least a first bend point is formed at a position smaller than a thickness of the substrate from the bottom surface of the package. As a result, where the leads of the photointerrupter are inserted into and soldered to a printed substrate or the like, soldering is possible without causing inclination or positional deviation.

Abstract: A reticle has a transfer region and a peripheral region defined in the plane of the reticle, the transfer region being formed with a pattern to be transferred and the peripheral region being disposed surrounding the periphery of the transfer region. Reference marks for defining one virtual reference line is formed in the plane of the reticle. A transfer pattern is formed in the transfer region and includes a long linear line segment oblique to the reference line. A pair of direction designating marks is disposed in the peripheral region along a virtual straight line parallel or perpendicular to the linear line segment of the transfer pattern.

Abstract: The electronic device has a structure that a semiconductor package is mounted on a mother board. To relieve stress caused by cyclic thermal load and applied to solder bumps that are electrically and mechanically connect the semiconductor package and the mother board, a shape-holding plate (stiffener) adhered to a wiring film is composed of a metal with a thermal expansion coefficient of 13.times.10.sup.-6 to 17.times.10.sup.-6 almost close to that of a glass-epoxy wiring substrate as the mother board. Examples of the metal are 25Cr-20Ni stainless steel or copper alloy containing 0.01 to 0.03% by weight of Zr.

Abstract: In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Abstract: A semiconductor package in which a semiconductor chip 16 is formed above a die pad 12 interposing a capacitor 22 therebetween, or the semiconductor chip 16 and the capacitor 22 in a vortex-shaped form are respectively formed on both faces of the die pad 12, or the condensers 22 are formed on both faces of the die pad 12 and the semiconductor chip 16 is formed on one of the condensers 22, and the die pad 12, the semiconductor chip 16 and the condensers 22 are sealed by resin by which adverse effect of noise is reduced, wherein the shape of the capacitor may be in a vortex-shaped form or opposed faces of metal layers may be roughened.

Abstract: A method for fabricating a semiconductor device of the invention, the method includes the steps of: providing an oxygen concentration in a region of a silicon film of 1.times.10.sup.18 cm.sup.-3 or less; depositing a film including a metal on the silicon film; and reacting the silicon film with the film including a metal so as to form a metal silicide film in the region of the silicon film.

Abstract: In a lead frame formed out of at least one metal selected from the group consisting of nickel and nickel alloys, copper and copper alloys and iron and iron alloys, the inner lead part is provided with a surface treatment layer of Ag or an alloy containing silver and the outer lead part is provided at least with a surface treatment layer of an alloy containing silver and tin of the body-centered cubic structure preferentially oriented in the (101) plane and/or the (211) plane. According to the above-mentioned structure, a semiconductor device that uses a lead frame for electronic parts which does not contain lead, one of the environmentally harmful pollutants, has good characteristics including solder wettability and bonding strength and is of low cost and a process for producing the device are provided.

Abstract: Methods of forming flip chip bumps and related flip chip bump constructions are described. In one implementation, a bump of conductive material is formed over a substrate. At least a portion of the bump is dipped into a volume of conductive flowable material, with some of the flowable material remaining over the bump. The remaining flowable material over the bump is solidified and includes an outermost surface the entirety of which is outwardly exposed. In another implementation, the outermost surface include an uppermost generally planar surface away from the substrate. The solidified flowable material together with the conductive material of the bump provide a bump assembly having a height which is greater than the height of the original bump. The increased height is achieved without meaningfully increasing a width dimension of the bump proximate the substrate.

Abstract: Apparatus for retaining a semiconductor wafer in a semiconductor wafer processing system. The apparatus comprises a support pedestal for supporting the wafer, first and second coplanar electrodes in the support pedestal for creating a chucking force, a cathode electrode for establishing wafer processing conditions and a third gap fill electrode positioned vertically between the first and second electrodes, such that the gap fill electrode is radially coincident with the gap between the first and second electrodes. A method of making the wafer retaining apparatus may comprise the steps of depositing electrode layers over molten, drawn sapphire layers to form a unitary bipolar electrostatic chuck having a gap fill electrode spaced between a pair of bipolar chucking electrodes and an RF powered electrode and radially coincident with the gap between the bipolar chucking electrodes.

Abstract: A chip-on-chip integrated circuit package is disclosed. The device includes a substrate having a plurality of conductive landings disposed on a first surface thereof, a first die that is positioned over a substrate, and a second die that is mounted on the first die. The first die has a plurality of I/O pads that face away from the substrate. The second die includes a first set of contacts that mate with the conductive landings on the substrate and a second set of contacts that mate with the I/O pads on the first die. In a preferred embodiment, the first set of contacts on the second die take the form of a first set of solder bumps, and the second set of contacts on the second die take the form of a second set of solder bumps.

Abstract: A lead frame includes a conductive base plate having a first surface on which a semiconductor element is to be mounted and a second surface opposite to the first surface, a lead forming portion arranged on the first surface of the conductive base plate, in a concavity in the first surface through etching by masking at least the lead forming portion. The lead forming portions are coupled with one another, and are not independent. Thus, bending of the lead forming portion in a lead frame is avoided. A semiconductor device using the lead frame, and methods for manufacturing the lead frame are also disclosed.

Abstract: A semiconductor device assembly having a support such as a lead frame paddle comprises a coating thereon to reduce or eliminate the flow of die attach adhesive from under the die and over bond sites or encapsulation regions. Thus undesirable effects resulting from this flow of adhesive, such as wire bonding problems and encapsulation problems, are reduced. A method for forming the assembly is also described.

Abstract: A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.