Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.

Abstract: A component for making microelectronic units includes a grid of interspersed leads with ends of the various leads being connected to one another by frangible elements. One end of each lead is bonded to a top element and the other end of each lead is bonded to a bottom element. The top and bottom elements are moved away from one another, thereby breaking the frangible elements and deforming the leads towards a vertically extensive disposition. A flowable composition such as dielectric material may be injected around the leads during or after the moving step. The resulting unit may be used to form permanent or temporary connections between microelectronic elements.

Abstract: Disclosed are a chip size stack package, a memory module having the same and a method for fabricating the memory module. In the chip size stack package, two semiconductor chips are arranged in a manner such that their surfaces on which bonding pads are formed, are opposed to each other at a predetermined interval. Insulating layers are applied to the surfaces of the semiconductor chips on which surfaces the bonding pads are formed, in a manner such that the bonding pads are exposed. Metal traces are respectively deposited on the insulating layers and connected to the bonding pads. Solder balls electrically connect the metal traces with each other. One ends of metal wires are bonded to a side of one of the metal traces. Both sides of the semiconductor chips and a space between them are molded by an encapsulate, in a manner such that the other ends of the metal wires are exposed.

Abstract: The present invention is an semiconductor device on a semiconductor substrate and a method for forming an semiconductor device on a semiconductor substrate. The semiconductor device in the present invention comprises a first metal layer, a first diffusion barrier layer on the first metal layer, a second metal layer on the first diffusion barrier layer, an organometallic layer on the second metal layer, and an electrical interconnect layer on the organometallic layer. The first diffusion barrier layer prevents diffusion of the first metal layer and the second metal layer therethrough. The organometallic layer is preferably formed by contacting the second metal layer with an organic material to form a organometallic layer. The organometallic layer chemically and physically protects the second metal layer, particularly by preventing the oxidation thereof.

Abstract: A semiconductor component has one or more semiconductor chips with contact pads, a number of substrate layers, component contacts and conductor tracks which establish the electrical connection between the contact pads of the semiconductor chip and the component contacts. The substrate layers are respectively provided with conductor tracks and at least one opening and the chip or chips are placed in the opening. A plurality of substrate layers are interconnected lying above one another. The conductor tracks of respective substrate layers end in an area in the vicinity of the at least one semiconductor chip and in an edge area of the respective substrate layer.

Abstract: A semiconductor device of the present invention comprises a mounting substrate, a supporting substrate, a die and a plurality of electrical conductors. The mounting substrate including a first surface and a second surface opposite to the first surface on which electrical traces are disposed is formed with a receiving hole passing through the first surface and the second surface. The supporting substrate is made of a metal material and the shape of the supporting substrate being accommodated to the receiving hole of the mounting substrate, the supporting substrate received in the receiving hole of the mounting substrate to form at least one die receiving cavity between peripheral wall confining the receiving hole of the mounting substrate and the supporting substrate. The die includes a pad mounting surface provided with a plurality of bonding pads and are received in the die receiving cavity.

Abstract: An IC card comprises: a plane coil having respective terminal sections; a semiconductor element arranged at a position not overlapping with the plane coil, the semiconductor element having electrode terminals; means for electrically connecting the respective terminal sections of the plane coil to the electrode terminals of the semiconductor element; and a reinforcing frame arranged on a face substantially the same as that of the semiconductor element so that the semiconductor element is surrounded by the reinforcing frame.

Abstract: A resin encapsulated semiconductor package, which uses leads (lead frame), and enhances heat conducting properties and prevents breaking of lengths of bonding wire, reduction in service life of solder joints and crack of a resin while ensuring reliability on strength. A lead material uses a material containing as a main constituent material a composite alloy of Cu2O and Cu, which has a thermal conductivity as high as that of copper alloys having been conventionally used, and which is sintered to have a small linear expansion coefficient as compared with such copper alloys.

Abstract: A leadframe for use with integrated circuit chips Comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment; and a plated layer of solder on said nickel layer, selectively covering areas of said leadframe intended for parts attachment.

Abstract: A solderable back contact for semiconductor die consists of a titanium layer bonded to the bottom of the die. The free surface of the titanium layer is coated with a copper layer. A soft solder layer joins the bottom of the die to a copper lead frame by first heating the die to below the melting point of the solder, and then ultrasonically “scrubbing” the solder to cause it to bond to the die and lead frame with a minimum sized solder fillet.

Abstract: An optoelectronic structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: A microelectronic package comprising a microelectronic element, resilient element including one or more intermediary layers capable of being wetted and assembled with the microelectronic element, and an adhesive is provided. The adhesive contacts at least one of the one or more intermediary layers and the microelectronic element. A resilient element is also provided.

Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.

Abstract: A semiconductor device has an interconnection pattern that crosses a vertical step. The part of the vertical step crossed by the interconnection pattern includes a horizontal side-step. The horizontal side-step increases the total length of the crossing, thereby reducing the risk of electrical discontinuity at the crossing, without increasing the width of the interconnection pattern itself.

Abstract: An electronic structure bondable to an electronic assembly, such as a chip. The electronic structure may be joined to a electronic assembly, such as a chip, by use of a structural epoxy adhesive. The electronic structure includes a mineral layer on a metallic plate, and an adhesion promoter layer on the mineral layer. The metallic plate includes a metallic substance that includes a pure metal with or without a metal coating. The metallic substance may include such substances as stainless steel, aluminum, titanium, copper, copper coated with nickel, and copper coated with chrome. The mineral layer includes a chemical compound derived from a mineral; e.g., silicon dioxide (SiO2) derived from quartz. Such chemical compounds may include such substances as silicon dioxide, silicon nitride, and silicon carbide. The chemical compound may exist in either crystalline or amorphous form. The adhesion promoter may include such chemical substances as silanes, titanates, zirconates, and aluminates.

Abstract: A mounting structure is formed by flip-chip mounting a semiconductor device onto a substrate. An electrical connecting portion of the semiconductor device is connected to an electrical connecting portion of the substrate by means of an electrically conductive adhesive. A region of the semiconductor device which is not involved in electrical connection is bonded to a region of the substrate which is not involved in electrical connection by means of an adhesive. A test of electrical properties is performed on the semiconductor device and the substrate which are connected to each other. If it is determined that the electrical properties are poor in the test, the semiconductor device is separated from the substrate after heating a bonding place of the adhesive up to a temperature higher than a glass transition point or a melting point of the adhesive. If it is determined that the electrical properties are good in the test, the semiconductor device and the substrate are sealed by means of a sealing resin.

Abstract: A semiconductor package and a method of making the package are disclosed. The package includes a semiconductor chip having first surface with a conductive pad thereon. A first end of a bond wire is connected to each of the pads. Encapsulant covers the fist surface of the chip, the pads, and the bond wires, and forms side surfaces of the package. A second end of the bond wires is exposed at a side surface of the package. Making the package includes providing a wafer including a plurality of semiconductor chip units. Each chip unit has a plurality of conductive pads at a first surface of the wafer. A bond wire is electrically connected between each pad of each semiconductor chip unit and a pad of at least one adjacent semiconductor chip unit of the wafer. An encapsulant is applied onto the first surface of the wafer so as to completely cover the bond wires and pads of the semiconductor units.

Abstract: In this semiconductor device, immediate below a mold line M in a surface where an inner lead of a wiring substrate composed of a BT resin impregnated glass cloth or the like is formed, a second solder resist layer is stacked on a first solder resist layer to form a protrusion of a predetermined width. Then, on a predetermined position of the wiring substrate, a semiconductor element is assembled by wire bonding and an assembled part thereof is molded by a resin layer. Further, on the other surface of the wiring substrate, bumps are formed. Such a semiconductor device is separated by use of a slit hole formed on the wiring substrate in advance in conformity with a mold line M. In this structure, in a step of molding, since a resin is not forced outside of a pushing face of a metal mold to form a burr or the like, a thin and small resin molded semiconductor device of excellent appearance and characteristic can be obtained.

Abstract: A semiconductor device, especially a Ball Grid Array or Chip Scale Package, comprising an integrated circuit chip having at least one input/output terminal; a body of encapsulation material molded around said chip, forming a generally flat surface including at least one dimple having a suitable size and shape to receive a solder ball or solder paste; and said dimple having an electrically conductive solderable surface connected to said terminal.

Abstract: A semiconductor device comprising a thermally conductive foil including a chip mount portion having first and second surfaces; an integrated circuit chip attached to said first surface; a body of encapsulation material molded around said chip and said first surface such that it leaves said second surface exposed; and said second surface comprising means for forming thermal contact, thereby creating a path for dissipating thermal energy from said chip. Said means for thermal contact comprise a configuration of said second surface suitable for direct thermal attachment to a heat sink. Alternatively, said means for thermal contact comprise a configuration of said second surface suitable for thermal attachment including solder balls between the chip and the heat sink.