Abstract: A connection between a contact plug and an interconnect in a semiconductor device is disclosed. A contact plug is formed in a hole within an insulating film with its upper and generally in flush with a surface of the interlayer insulating film. An Interconnect uses a laminated film structure that includes an aluminum film over the upper end of each of the contact plug.

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract: A semiconductor device with a multi-level interconnection structure has a first conductive layer disposed below a fuse, and formed in the same layer as the first metal wire as a component of multi-level interconnects, and a second conductive layer disposed below the fuse and formed in the same layer as the second metal wire as a component of the multi-level interconnects. A laser beam control unit is configured with the first and second conductive layers. Thus, damage occurrence in a semiconductor substrate may be controlled during blowing the fuse, a quality deterioration and further a defective of the semiconductor device may be not only avoided, but also an integration degree thereof may be enhanced.

Abstract: A flip chip having solder bumps, an integrated underfill, and a separate flux coating, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required a separate underfilling step.

Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost.

Abstract: A ceramic column grid array package suitable for mounting application specific integrated circuits or microprocessor chips onto a printed circuit board employing polymer reinforced columns on the substrate module is described. The polymer enhancement is formed by coating a thin conformal film of a polymer, such as, a polyimide onto the substrate module after the formation of the ceramic column grids to mechanically enhance the column to substrate attachment of the column to the substrate prior to mounting on a printed circuit card. Upon curing of the polymer film at a temperature below the melting point of the solder bond attaching the column grid to the substrate, the columns will be mechanically reinforced in their attachment to the substrate. Upon removal of the substrate module from a printed circuit card during rework, the columns of the grid array will remain with the substrate module, leaving no columns on the printed circuit card.

Abstract: The invention relates to a self-centering arrangement of microstructured elements, particularly of microoptical components on a substrate serving as carrier. To provide microoptical components with projections that fit into corresponding recesses is known in the art. The invention provides a way to improve the mutual alignment of components (K1, K2) in that a deformation occurs when projections (Z1, Z2) are inserted into the recesses (A). This deformation may concern the projections or the recesses themselves or a molding material introduced between the projections and the recesses. The deformation improves the self-centering properties; in addition, manufacturing tolerances are more easily compensated. If the element cannot be provided with a suitable projection, an intermediate carrier is used, which is, for example, a plastic element produced by a LIGA process.

Abstract: A rigid encapsulation package for semiconductor sensors, actuators, and devices is described. In one embodiment, a semiconductor pressure sensor includes a sensor element having a deformable diaphragm for measurement of pressure, and a cap that includes a recess. The cap is attached to the sensor element to form a cavity therebetween. The pressure sensor further includes a leadframe, interconnecting bond wires, a pressure port that is coupled to the sensor element, and a nominally rigid material formed over the sensor element, cap, leadframe, and bond wires. The material may include one or more of the following: epoxy, RTV, resins, and gel. The sensor element may include a built-in stress isolation flexible region. A second pressure port may optionally be attached to the housing for providing differential or gage pressure measurements.

Abstract: A contact structure for achieving an electrical connection with a contact target is formed by producing contactors on a semiconductor substrate by a microfabrication technology. The contact structure is formed of a contact substrate and a plurality of contactors mounted on the contact substrate. Each of the contactors has a sphere contact to contact with the contact target when the contact structure is pressed against the contact target. A spring force is generated when the contactor is pressed against the contact target. Various types of contact structures and the production method thereof are also described.

Abstract: A semiconductor device having a plurality of crystalline silicon clusters. The semiconductor device is formed on an insulating surface and includes crystalline silicon clusters anchored with each other with substantially no grain boundary therebetween.

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of an opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface for the semiconductor chip.

Abstract: A mold compound made from a polymer resin and an isorefringent, transparent filler is used to form optical electronic components (10, 20, 30). The mold compound can be used to form a lens (13) on a display device (10), to form the outer housing (21) of a waveguide (20), or to form a dome (34) that reflects light from a light emitting device (32) to a light detecting device (33).

Abstract: An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.

Abstract: A multichip semiconductor device comprises a plurality of semiconductor chips, each including elements integrated in a semiconductor substrate. The semiconductor chips have substantially the same structure. Each semiconductor chip includes a connecting plug inserted in a through hole made through the semiconductor substrate. The semiconductor chips are stacked in layers. The connecting plugs of the semiconductor chips are selectively connected through metal bumps. Allocation of addresses of the semiconductor chips is designated by a connecting pattern of the bumps.

Abstract: A lead frame for a chip package includes a heat spreader and permits the mounting of various sized chips on the same sized lead frame. The lead frame includes a plurality of leads having outer portions and inner portions; a heat spreader having a rim portion adapted to be attached to ends of the inner portions of the leads and a projecting portion that projects between the ends of the inner portions of the leads such that an upper surface of the projecting portion is in approximately the same plane as an upper surface of the inner portions of the leads. An insulative adhesive may be used to attach the ends of the inner portions of the leads to the rim portion of the heat spreader. Also, insulation members may be attached to upper surfaces of the ends of the inner portions of the leads for receiving a large size chip.

Abstract: A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.

Abstract: An integrated circuit package which includes an integrated circuit that is connected to a silicon substrate. The silicon substrate may have a via. The package may further include a solder bump that is attached to both the integrated circuit and the silicon substrate. The silicon substrate has a coefficient of thermal expansion that matches the coefficient of thermal expansion of the integrated circuit.

Abstract: According to the present invention, a contact hole is formed by using a contact formation mask until portions of a first and a second impurity areas are respectively exposed, so that contact holes are formed. The size of the contact hole formed over the first impurity area (P-type impurity) is relatively larger than that of the contact hole formed over the second impurity area (N-type impurity). As a result, the size of the contact hole formed over an N-type impurity area decreases and that of the contact hole formed over a P-type impurity area increase to a corresponding degree, thereby reducing contact resistance generated on the P-type impurity area without increasing a chip size.