Patents Examined by Jigar Pancholi
  • Patent number: 6148417
    Abstract: One embodiment of the present invention provides a method for determining a source of failure during a failed file access in a computer system. This method generates a sequence of file references from a first location in the computer system, and maintains a record of parameters specifying the sequence of file references. The results of the sequence of file references are examined to detect a failure during a file reference. If a failure is detected, the failed file reference is reconstructed using the record of parameters, and is then retried to determine the source of failure. In between retries, the method allows various system components to be manipulated to isolate the source of failure. In one embodiment, these manipulations include: replacing hardware components; replacing system firmware; replacing software components; and inserting debug code into a program on the computer system.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: November 14, 2000
    Assignee: Micron Electronics, Inc.
    Inventor: Luis A. da Silva
  • Patent number: 6145029
    Abstract: A computer system including a programmable bridge logic device to disable various peripheral device functions is disclosed. The bridge logic device preferably includes an address decoder and one or more peripheral bus controllers. The address decoder preferably includes a configuration disable unit comprising one or more programmable status bits. Each status bit is associated with a particular peripheral device function, such as a IDE or USB functions. When a status bit is set, configuration cycles to the function corresponding to that bit are disabled. In one aspect of the invention, the computer system comprises a laptop computer that can be docked to an expansion base. The laptop and the expansion base may duplicate one or more functions. When docked, the status bit in the bridge device associated with a function also provided in the expansion base is set disabling the duplicate function in the laptop in favor of the function in the expansion base.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: November 7, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Todd Deschepper, Paul Stanley
  • Patent number: 6119177
    Abstract: In an ATAPI device and method for interfacing a digital video disk signal processor with a data processor, a digital video disk ROM interfacing apparatus controls data transmission from the digital video disk signal processor to the ATAPI interfacing apparatus such that a plurality of bytes of data are transmitted for each data transmission request. In the digital video disk ROM interfacing apparatus, a byte designator stores a number of designated units which is the number of data units which are to be transmitted once. A counter up-counts when a data unit is transmitted and outputs a number of transmitted units. A comparator compares the number of designated units output by the byte designation means with the number of transmission units output by the counter. A data request signal generator requests data transmission to the digital video disk signal processor according to a comparison result from the comparator.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: September 12, 2000
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Jeh-won Kim
  • Patent number: 6105096
    Abstract: A simple connection arrangement is provided for inter-communicating a portable computer and a desktop computer. Each computer is provided with a 2:1 optical coupler for transmitting and receiving signals to/from a duplex fiber-optic cable used to interconnect the computers. The cable is unpluggable at one or both ends and avoids crossover problems. A standard protocol can be operated across the link established by the fiber-optic cable. The desktop computer preferably includes functionality enabling communication to be extended into a connected computer network.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: August 15, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Rene Martinelli, Gregory Mathes
  • Patent number: 6092131
    Abstract: A method for automatically terminating a bus that is dependent upon whether devices are coupled to ports of a device interface is disclosed. The method includes the steps of (a) generating a first sensing voltage having a voltage level equal to one of at least three levels; (b) generating a first control voltage having a fourth level when the voltage level of the first sensing voltage has a first predetermined logical relationship to a first reference voltage; and (c) terminating a first plurality of lines of the bus at the device interface when the first control voltage is equal to the fourth level. An apparatus suitable for implementing the above method is also disclosed.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: July 18, 2000
    Assignee: LSI Logic Corporation
    Inventors: Barry E. Caldwell, Christopher B. Ross
  • Patent number: 6092219
    Abstract: A system for flexibly and efficiently communicating diagnostic information about an integrated ASIC device. Where the ASIC is associated with a PCI bus, the bus parking or idle state for the PCI bus is used for placing status or diagnostic information relating to or about the ASIC on the PCI bus. This information can then be observed and used in a debugging process.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: July 18, 2000
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 6092197
    Abstract: System and method of discovering and exploiting information such as private or confidential facts from a user, while securing the information from unauthorized publication includes, a sender having a processing module transmitting a request for publication of information about a user; an agent in communication with the sender receiving the request for the information, and a user in communication with the agent responding to prompts initiated by the agent. The prompts request the user to reveal facts relating to the information desired by the sender, and provide indicia relating to authorization for publication of the disclosed facts to the sender. The agent discovers the facts and determines whether such facts are to be made available to the sender.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: July 18, 2000
    Assignee: The Customer Logic Company, LLC
    Inventor: Philippe Coueignoux
  • Patent number: 6085328
    Abstract: A reliable and simple means to awaken sleeping computers is to maintain the network interface subsystem at full power, and to filter detected packets so that when desired packets are detected, full power is restored to the entire computer. An interface to connect a computer to a network is provided, where, the computer has a high power state and a low power state, and the computer is capable of normal operation when in the high power state, and the computer is substantially inactivated when in the low power state. A packet is received from the network. The packet is filtered by computing a hash function using at least one byte selected from the packet. A transition is initiated, responsive to a result of filtering the packet, to transition the computer from the low power state to the high power state. A mask may be used to select the at least one byte. Several bytes may be selected by the mask. A first register may be used to hold the mask.
    Type: Grant
    Filed: January 20, 1998
    Date of Patent: July 4, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Philippe Klein, Simoni Ben-Michael
  • Patent number: 6079034
    Abstract: An automatic loop-elimination system embodied in a network hub minimizes the impact of port deactivation by deactivating only one port at a time. To reduce the likelihood of concurrent examination of ports (of different hubs) coupled to other hubs, the port at which examination begins is randomized at network startup. To reduce the likelihood of concurrently examined ports (of different hubs) being deactivated at the same time, a brief re-poll of port utilization is run just before deactivation; if the first deactivation eliminates the loop, the second port is not deactivated. For each hub, the method cycles through the ports three times, progressively including more heavily cascaded ports. This progressive relaxation of a cascade constraint preferentially deactivates ports coupled to end-node devices before ports coupled to other hubs. Thus, the invention provides for fast and convenient automatic loop elimination without requiring external hardware or software.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: June 20, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Craig A. VanZante, Robert L. Faulk, Jr., Douglas E. O'Neil
  • Patent number: 6079020
    Abstract: The present invention provides a method and an apparatus for managing a virtual private network operating over a public data network. This public data network has been augmented to include a plurality of virtual private network gateways so that communications across the virtual private network are channeled through the virtual private network gateways. One embodiment of the present invention includes a system that operates by receiving a command specifying an operation on the virtual private network. The system determines which virtual private network gateways are affected by the command. The system then automatically translates the command into configuration parameters for virtual private network gateways affected by the command. These configuration parameters specifying how the virtual private network gateways handle communications between specific groups of addresses on the public data network.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: June 20, 2000
    Assignee: VPNet Technologies, Inc.
    Inventor: Quentin C. Liu
  • Patent number: 6076133
    Abstract: The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons is connected to at least two wires, with the depression of a button causing an electrical connection between the corresponding two wires. The voltage on one of these wires is forced to a steady-state logic low, while the voltage on the other wire is allowed to float electrically free. Nonetheless, the second wire is at a steady-state high voltage due to that wire's connection through a pull-up resistor to a voltage source. Upon electrical connection, the wire that is floating free acquires a logic low voltage. In response, a line state detector sends an interrupt signal to a microprocessor, which transitions the voltage on the wires forced to a steady-state logic low from a logic low to a free floating state.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: June 13, 2000
    Assignee: Compaq Computer Corporation
    Inventors: James W. Brainard, Mark E. Taylor, Larry W. Kunkel, Stephen A. Walsh, Michael A. Provencher
  • Patent number: 6076112
    Abstract: In a link-level flow controlled system, a method and apparatus providing the ability to partition a buffer resource among multiple prioritized buffer subsets through definition of at least one threshold, the buffer resource being shared by a plurality of connections. Different category of service levels, in terms of delay bounds, are thus enabled. The presently disclosed link-level flow controlled system provides for zero cell loss. The shared buffer resource is divided among N priority pools, defined by N-1 threshold levels, each priority pool attributable to a respective category of service. Link-level counters and registers, disposed in a transmit element, as well as an indication of priority level associated with each connection, are employed in realizing the shared buffer resource.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: June 13, 2000
    Assignees: Fujitsu Network Communications, Inc., Fujitsu Limited
    Inventors: Stephen A. Hauser, Stephen A. Caldara, Thomas A. Manning
  • Patent number: 6070215
    Abstract: A computer system includes a South bridge logic device that monitors the FLUSHREQ signal and masks that signal when the CPU transitions the computer to a low power mode of operation. Once masked, the FLUSHREQ cannot be asserted to the North bridge and the conflict between attempts by the CPU and an ISA device to run cycles on the PCI bus is avoided. The South bridge also masks all requests to run cycles on the PCI bus that are not originated by the CPU. The South bridge includes a programmable control register and a PCI arbiter. When a control bit is set in the register, the PCI arbiter waits for FLUSHREQ to be deasserted and then masks FLUSHREQ. The PCI arbiter preferably also disables PCI arbitration by masking all non-CPU. Only the CPU can run PCI cycles when the non-CPU requests are masked. The programmable control register also includes a masking status bit that is set when both the FLUSHREQ and non-CPU request signals are masked by a request mask state machine.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: May 30, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Todd J. Deschepper, Robert C. Elliott
  • Patent number: 6067593
    Abstract: A universal memory bus coupled between a system's CPU and the system memory is composed of four channels; a primary channel, an identification channel, a programming channel and an expansion channel. The primary channel communicates operating system data necessary to boot the system. The identification channel communicates signals describing the device composition of the system memory. The programming channel communicates programming signals to all of the programmable memory devices within the system memory and thus allows complete programmability of those devices. The expansion channel provides data and programming access to a memory device subsequently added to the system memory.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: May 23, 2000
    Assignee: Avido Systems, Inc.
    Inventor: Peter Arthur Schade
  • Patent number: 6065082
    Abstract: Communication, using a synchronous protocol, over a synchronous communications link, between synchronous application programs executed on a terminal (i.e., personal computer, PC) with an asynchronous byte-oriented interface and a PC with a synchronous frame orientated interface is made possible by enhancing the PC with the asynchronous byte-oriented interface with a device which modifies the data to be transmitted by inserting framing flags and transparency characters before the data passes through the COMM port (asynchronous byte-oriented interface) and extracting the transparency characters after the data exits the COMM port. As a consequence, the PC with the frame-oriented interface does not have to be modified.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: May 16, 2000
    Assignee: International Business Machines Corporation
    Inventors: Dana Lynn Blair, Gordon Taylor Davis, Cloyd Stanley McIlvaine
  • Patent number: 6061756
    Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: May 9, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Drew J. Dutton, Scott E. Swanstrom, J. Andrew Lambrecht
  • Patent number: 6055596
    Abstract: A method for use in a computer system having buses identifiable by bus identifiers and having an expansion card slot capable of being connected to one of the buses and capable of receiving an expansion card. The method includes assigning the bus identifiers to the buses according to an assignment sequence. The method determines if there is an expansion card that can be accessed via the slot. If not, at least one of the bus identifiers for the slot is reserved in accordance with the assignment sequence. Memory space and I/O space may also be reserved for the slot if the expansion card cannot be accessed.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: April 25, 2000
    Assignee: Compaq Computer Corp.
    Inventor: Darren J. Cepulis
  • Patent number: 6055584
    Abstract: A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: April 25, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey Todd Bridges, Edward Hammond Green, III, Richard Gerard Hofmann, David Otero, Mark Michael Schaffer, Dennis Charles Wilkerson
  • Patent number: 6055636
    Abstract: A method and apparatus for centralizing the processing of key and certificate life-cycle management is accomplished when security activation of a communication device has been detected. Security activation may occur at log-on of the secure communication device (e.g., a personal computer equipped with a security application, or applications), at activation of a security application, or at re-authentication of a security application. Once the security activation has been detected, the secured communication device accesses a depository of security information to retrieve relevant security information. The secured communication device then interprets the relevant security information to determine when local security parameters are to be changed. When local security parameters (e.g., encryption key pair, a corresponding encryption public key certificate, a signing key pair, and/or a corresponding verification public key certificate) are to be changed, the local security parameters are updated.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: April 25, 2000
    Assignee: Entrust Technologies, Limited
    Inventors: Stephen William Hillier, Ramon Jonathan Lee Dilkie, Gerrard Eric Rosenquist
  • Patent number: 6052513
    Abstract: Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: April 18, 2000
    Assignee: Compaq Computer Corporation
    Inventor: John M. MacLaren