Abstract: A bus controller controls access to a computer bus by a plurality of bus requesters. The bus controller activates a priority bus request line on the computer bus regardless of which of plural priority bus agents desires to transmit a transaction on the computer bus. The bus controller receives an I/O request signal from a bus agent and determines whether the priority bus request line is in an active state. If the priority bus request line is not in the active state, then the bus controller activates the priority bus request line in response to the I/O request signal. If the priority bus request line is already in the active state, then the bus controller leaves the priority bus request line in the active state for a time period sufficient to enable the bus agent to transmit a transaction on the computer bus. In addition, the bus controller transmits an I/O grant signal to the bus agent to enable the bus agent to transmit the transaction on the computer bus.

Abstract: A computer system, and particularly a handheld mobile client system, in which an energy management control program having a plurality of cooperating components permits a designer to choose from among a plurality of foci for energy management.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems. In various embodiments, multimedia devices transmit addressing and control information for a multimedia bus transfer either over the PCI bus or using a separate serial control channel. The multimedia bus may also comprise separate multimedia channels for different data types.

Abstract: A bus arbitration method for use in a multiprocessor system having a plurality of agents and a system bus, for determining a sampling point at which bus arbitration-related signals on the system bus are latched and arbitration-related signals on the system bus based on the latched arbitration-related signals, each of the bus arbitration-related signals representing a bus request signal asserted on the system bus by one of the agents for gaining an access to the system bus, wherein the system bus is arbitrated during an arbitration period in synchronization with a bus clock signal formed by a train of clock pulses generated at each clock period, the arbitration period being greater than N but not greater than (N+1) clock periods with N being a positive integer. At a first step, an initial sampling point is set at a predetermined point on a clock pulse.

Abstract: A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.

Abstract: A bus to bus bridge deadlock prevention system detects and resolves a deadlock condition in a bus to bus bridge. In a PCI protocol application of the present invention, the system detects a retry of a request by a master device. The request is masked for a delay period before the request is allowed to attempt to pass through a PCI to PCI bridge. If the request results in a further retry, the delay period length is changed and the request is masked for the different delay period. Successive retry requests are masked for different delay periods until the deadlock condition is resolved. The system adapts to the deadlock condition by repeatedly changing the delay period until the deadlock condition is resolved and the bridged busses resume normal operation.

Abstract: The invention encompasses a system that utilizes radio frequency circuitry in combination with microprocessor devices and specially designed software to provide an improved structure and operation for the monitoring, protection and control of inventory assets. Generally, the system is embodied in a system controller unit, one or more interrogator devices and multiple transponder units. The system controller unit may be a personal computer (PC) based device for effecting the control and monitoring of the system's operation. In addition, the system controller unit serves as a data collection device and as an alarm device. The interrogator device(s) incorporate a transceiver controlled by microprocessor circuitry within the interrogator devices. The transponder units also include a radio transceiver and microprocessor circuitry. The transponder units are attached to a container or item to be monitored and protected.

Abstract: Method and apparatus for detecting the presence of a semi-compliant PCI device in a secondary expansion slot of a PC and instructing the user to reinsert the device into one of the primary slots are disclosed. In one embodiment, upon detection of a semi-compliant PCI device in a secondary slot, a video image instructing the user to reinsert the device into one of the primary slots is displayed on a display of the PC. Operation remains suspended until the device is relocated to a primary slot. In a presently preferred embodiment, a hardware enhancement to a PCI-to-PCI bridge connecting a primary PCI bus to a secondary BCI bus enables the device to operate flawlessly on the secondary PCI bus, such that the user remains unaware of the otherwise undesirable situation.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: A method for processing interface messages, such as SCSI messages, using an indexed jump table. Two single-dimensional tables are implemented by the method described. The first table stores index values for all valid sequence instruction locations for which an ATN signal can be detected. The second table stores index values for all valid interface messages. The index values of these two tables are used as entry points to the indexed jump table whose elements contain addresses to message handling functions.

Abstract: Communication, using a synchronous protocol, over a synchronous communications link, between synchronous application programs executed on a terminal (i.e., personal computer, PC) with an asynchronous byte-oriented interface and a PC with a synchronous frame orientated interface is made possible by enhancing the PC with the asynchronous byte-oriented interface with a device which modifies the data to be transmitted by inserting framing flags and transparency characters before the data passes through the COMM port (asynchronous byte-oriented interface) and extracting the transparency characters after the data exits the COMM port. As a consequence, the PC with the frame-oriented interface does not have to be modified.

Abstract: An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

Abstract: A method and apparatus for transferring data from a first bus to a second bus. A bridge couples a first bus to a second bus. The bridge includes a buffer to store two data elements of a first packet transferred to the buffer from the first bus. The bridge also includes a controller that permits a first data element to be transferred from the buffer to the second bus. In addition, if at least a portion of a second packet has not been transferred to the bridge from the first bus, then the controller causes at least one wait state to be inserted on the second bus before transferring the second data element of the first packet from the buffer to the second bus.

Abstract: A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An unique interrupt identification code is assigned to each interrupt request and used to reference information in the storage device associated with each interrupt request. The interrupt request interface uses the unique interrupt identification code to access the information for each interrupt request and determine if the interrupt request should proceed to one of the processor interfaces. The processor interface uses the unique interrupt identification code to access the information in order to determine if and when the interrupt request should issue to one of the CPUs.

Abstract: A computer system that automatically and securely executes registered programs immediately prior to a transition to a reduced energy consumption state. A registrar table specifying registered programs and a secure modification detection value for each registered program are maintained in system management mode memory or other secure memory space in the computer system. A system management interrupt is generated following a request to remove power from the computer system or the occurrence of an event that triggers an energy saving mode. The system management interrupt handler routine then generates a current modification detection value for each registered program. The current modification detection values are compared with the secure modification detection values. Execution of a registered program is permitted if the values match. After all registered programs have been executed, the computer system automatically powers down or enters an energy saving mode.

Abstract: Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

Abstract: A computer has multiple PC Card slots, each capable of receiving a ZOOM video device and providing that device access to the frame buffer through a Video Feature Port (VFP) on the graphics controller. Additionally, a docking station may also access the frame buffer through the VFP. Access may be controlled by a variety of predetermined priority or user selection schemes.

Abstract: A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a serial link data transmission system for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel I/O interface.

Abstract: A speculative instruction queue for a superscalar processor of the type having a variable byte-length instruction format, such as the X86 format, is organized as a 16-byte FIFO. The head of the queue is always the beginning byte of an X86 instruction, and the queue always shifts by one or more X86 instruction boundaries as X86 instructions are decoded and dispatched. Each byte position within the queue includes a valid bit for indicating whether the byte position within the queue contains valid information, the raw X86 instruction byte as originally fetched from an instruction source and stored within a preceeding cache, and a group of predecode bits assigned to the raw X86 instruction byte when initially pre-fetched and cached, and which predecode bits indicate the starting byte, ending byte, and the opcode byte of an X86 instruction, as well as the number of internal RISC-like operations into which the corresponding X86 instruction is mapped.

Abstract: A bus controller controls access to a computer bus by a plurality of bus requesters. The bus controller activates a priority bus request line on the computer bus regardless of which of plural priority bus agents desires to transmit a transaction on the computer bus. The bus controller receives an I/O request signal from a bus agent and determines whether the priority bus request line is in an active state. If the priority bus request line is not in the active state, then the bus controller activates the priority bus request line in response to the I/O request signal. If the priority bus request line is already in the active state, then the bus controller leaves the priority bus request line in the active state for a time period sufficient to enable the bus agent to transmit a transaction on the computer bus. In addition, the bus controller transmits an I/O grant signal to the bus agent to enable the bus agent to transmit the transaction on the computer bus.