Abstract: Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

Abstract: A failure analyzer has an electric characteristic inspection system for producing pieces of electric test data information for integrated circuit devices fabricated on a semiconductor wafer, a visual inspection system for producing pieces of appearance test data information for the semiconductor wafer and a data analyzing system for producing a failure analysis report from the pieces of electric test data information and the pieces of appearance test data information, and the data analyzing system is implemented by using a client-server network technology so as to increase a data processing capability depending upon the amount of data to be analyzed.

Abstract: A method and apparatus for establishing and maintaining complex security rules is provided. The security rules are established through the use of "permission" classes that take advantage of the power and simplicity various features of object oriented programming, including the ability to inherit attributes and methods. For example, a permission super class is established that defines an interface to a validation method. A permission subclass may then be created which provides an implementation of the validation method. When invoked, the validation method indicates whether a given permission represented by one object belonging to a permission class encompasses the permission represented by another object belonging to a permission class. Classes are also provided for grouping permissions into sets, and for establishing protection domains for classes of objects.

Abstract: A method for transmitting data when a system detects the amount of data which can be transferred, and divides the data to be transferred into a plurality of data blocks to form a list. A transfer device refers to the list and carries out input and output processing between a VTR or a network and a memory. Thus, the data can be efficiently transmitted at high speed with high reliability and independent of system configuration. Additionally, the data can be rearranged in the course of its transmission.

Abstract: A computer display switching circuit employed in a computer system having an external display and a notebook computer having an internal display includes an external display sensor for checking the state of the external display connector to sense whether the external display is receiving an image signal, and an image signal output controller for controlling an image signal output according to the state sensed by the external display sensor. Accordingly, power to the external display connected to the notebook computer is turned on or off according to the opening and closing of the cover of the internal display of the notebook computer so as to avoid the need for a conventional keyboard hot key. Also, in the case that only an external display is used, the internal display is powered down. Therefore, unnecessary power consumption by the internal display is prevented.

Abstract: A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.

Abstract: A method of generating in a tertiary storage device a backup copy of data, the method including the steps of writing data to a first set of storage volumes; while data is being written to the first set of storage volumes, mirroring the contents of the first set of storage volumes into a second set of storage volumes; after an amount of data has been written to the first set of volumes, terminating the mirroring; while mirroring is terminated, continuing to write data to the first set of volumes thereby causing the second set of volumes to become unsynchronized from the first set of volumes; while the mirroring is terminated, backing up data stored in the second set of volumes to the tertiary storage device; after backing up the second set of volumes, resuming mirroring of the first set of volumes to the second set of volumes; and after resuming mirroring, incrementally resynchronizing the first and set sets of volumes with each other.

Abstract: A nonintrusive monitoring system is used to determine the onset and duration times of an electrical power outage-caused down condition of a computer without requiring a pre-power outage polling of a running component of the computer and thereby degrading computer system performance. In response to a supply power outage the monitoring system switches on a battery-powered counter device, representatively a digital counter or a real time clock, and then switches the counter device back off in response to resumption of power supply to the computer. A software portion of the monitoring system then detects the count value of the counter device, and utilizes the count value to compute the onset and duration times of the previous power outage.

Abstract: A system and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources wherein a predetermined priority level for each input port is maintained by each output port. When a conflict for a particular output port occurs, the priority levels of the conflicting inputs are evaluated and access is initially granted to the highest priority input. Once this initial access is granted, the priority level of the "winning" input is then changed to the lowest priority level and the priority of all of the other inputs is increased by one. Inputs not requiring access to a particular output port over a relatively long period of time will resultantly have their priority incremented to the highest level and remain there. If multiple inputs have been incremented to the highest priority, or another form of priority conflict occurs, the input may then default back to its original predetermined priority.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.

Abstract: A power management unit is provided that includes a plurality of configuration registers for storing configuration information to set various operational parameters of the power management unit. A program register is mapped within the configuration space of the computer system and is utilized to store a value which sets the I/O address of the index register. The program register is written during the initialization of the power management unit, and may be associated with a predetermined default value. Once the program register has been set with a value indicating the I/O address of the index register, accesses to the configuration registers are achieved by first writing an offset value to the index register. Subsequently, configuration data may be written into or read out of a designated configuration register by executing an appropriate cycle to the address of the configuration data register, which may be mapped one word location beyond that of the index register.

Abstract: An arbitration method for access to a serial bus includes the steps of monitoring for the presence of an arbitration reset gap on the serial bus, and arbitrating for an access, if needed, upon recognizing the presence of an arbitration reset gap on the serial bus. The method further comprises the steps of determining if immediately arbitrating for an additional access without waiting for the presence of another arbitration reset gap on the serial bus is authorized, upon successfully arbitrating for an access. If immediately arbitrating for an additional access is authorized, and the additional access is needed, arbitration for the additional access is immediately made. A method for controlling arbitration for access to a serial bus includes the step of programming bus agents with information for the bus agents to determine whether immediately arbitrating for additional accesses to the serial bus are authorized.

Abstract: A process transmitter communications circuit has link terminals which are coupled to a process link, which supplies power to the circuit. A power source is coupled to one of the link terminals and is independent from the power supplied from the process link. Communications circuitry is coupled to the power source and link terminals, which transmits a transmitter signal over the process link, through the link terminals. A power sensing component is coupled to at least one of the link terminals and the communications circuitry and senses whether the power supplied by the process link is inadequate to transmit the transmitter signal. A power control component is coupled to the power source, the link terminals and the communications circuitry and selectively applies power from the power source to the communications circuitry for transmitting the transmitter signal when the power sensing component senses there is inadequate power supplied by the process link.

Abstract: A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that control the power consumption of each. The power control register fields can be set by software which has the much greater ability to look out into the future to determine whether the functional units will be required. The functional units are responsive to the corresponding power control register field to adjust their rate of execution responsive to the value stored therein. The rate of execution can be controlled in a number of different ways: dividing down the clock; removing power to the functional unit; disabling the sensor and/or buffer driver of one or more of the ports in a multi-ported RAM; removing data from the functional unit; and changing the data bus width responsive to the control register field.

Abstract: The system described provides a reconfigurable serial interconnection among a processor, whether in a workstation or a server, and user class I/O devices, such as video display terminals, storage devices, and other peripherals. Sustainable I/O throughput of 1 Gbps or more supports the needs of display and video input devices. In addition the system allows hot plug-and-play of user class I/O devices.

Abstract: An interrupt scheme for a data processor includes an enable field for a non-maskable interrupt (NMI). The field is automatically cleared by the data processor when it services the highest priority interrupt, a RESET. The user can set the field to enable a subsequent NMI but cannot himself clear the NMI. This strategy prevents an NMI from interrupting a RESET service routine.

Abstract: An Internet accessing system which allows automatic user login onto the Internet with the use of two cards and card readers. One card contains information about an Internet access point telephone number, the ID number of the user, and the password of the user. The second card contains information about the URL designating the location of the desired startup homepage. Upon insertion of the cards into the card readers, the user is automatically logged onto the Internet.

Abstract: A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.

Abstract: A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a mesh or ring of rings topology. The data transfer network includes links or buses, and switchpoints. The links or buses are configured in a ring topology as a mesh or ring of rings with each group of links of bus including a portion which is shared with a portion of another group of links or bus. The bus switchpoints are positioned at intersections of the mesh of rings. Each switchpoint is operable to route data from a source to a destination so that the modules are operable to communicate with each other through the groups of links or buses, and switchpoints. In various embodiments, the modules are coupled to the links or buses and/or the switchpoints.

Abstract: A priority encoder for generating a priority-encoded address which identifies the highest priority request line. According to one priority scheme, the active request line having the lowest address has the highest priority. The priority encoder is capable of generating the priority-encoded address by determining information corresponding to the most significant bits of the priority-encoded address and using this information in the computation of less significant bits of the priority-encoded address. Using purely combinatorial logic, including switch elements, the priority encoder is capable of computing lower order bits using feedback signals resulting from the computation of higher order bits, allowing successive computation of priority-encoded address bits, without necessitating the use of clocks or delay elements.