Abstract: A computer has an AC power outlet, preferably a standard AC outlet, into which periperhal devices, such as video monitors, can be plugged. It can turn this outlet on and off under program control, preferably by writing an outlet control signal to an I/O port which controls the outlet. A activity monitor, preferably in software, generates outlet control signals when one or more of the computer's peripheral devices have been inactive for more than a predetermined time. In some embodiments, the activity monitor turn off different parts of the computer in response to different types of inactivity. Preferably the computer can turn off the AC outlet without turning off the computer as a whole, and preferably it turns off the AC power outlet when the computer is turned off. Normally the AC outlet and its switching circuitry are part of the computer's power supply.

Abstract: A host adapter, having at least two connectors which both belong to a single digital computer bus, includes a first terminator that is coupled to a first portion of the digital computer bus, and a second terminator that is coupled to a second, separate portion of the bus. Upon being enabled by a control signal, these terminators respectively terminate the first and second portions of the bus. The host adapter also includes termination control logic coupled to the first and second terminators, and to connectors for the bus. The termination control logic receives connection signals from the connectors which indicate connection or non-connection of a device to the first portion, or to the combined first and second portions of the bus. The termination control logic processes these connection sensing signals and transmits two independent control signals which appropriately enable or disable the first and second terminators.

Abstract: A raster imaging device with the capability of computing a storage or retrieval address of color components (channels) of each pixel "on-the-fly" as the data is stored into a color image memory or retrieved from the memory, respectively. This computation of the address allows simultaneous image data format conversion and image reorientation.

Abstract: A computer network includes a network server in communication with a plurality of user terminals. The network server includes disk drives which store data accessible via the user terminals. To increase power efficiency of the network server, the number of accesses to the disk drives is monitored and a histogram is generated to display the distribution of disk accesses over time. A network administrator subsequently selects time intervals to spin down one or more of the disk drives during periods of disk inactivity as depicted in the histogram. In a preferred embodiment, the network administrator uses the histogram for failure analysis to determine which disks are more likely to fail over long time periods.

Abstract: A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request.

Abstract: A media access scheduling system that allows concurrent users to access shared media by having each user decide, as it gets access to the media, whether it is the best candidate for the use of the media: if it is, it proceeds to use the media; if it is not, it does not access the media, but instead releases access reservation and waits for a time when it may be the best candidate. In a preferred embodiment, the determining factor for the best candidate is whether the media needs to be repositioned or setup. If the media is positioned where the candidate wants it to be, no positioning or setup is required, and the user declares itself to be the best choice. If the media must be repositioned or setup, then there is probably another user process which would be a better candidate. To identify when a user is finished with the media and repositioning or setup is warranted, each user program refers to and maintains an access time in a globally visible place.

Abstract: A method and apparatus for use in transmitting information on a wired-OR signal line is described which employs a data transfer protocol exploiting the generally shorter signal settling time occurring following high to low signal voltage transitions than occurs following low to high signal voltage transitions. In accordance with the protocol, the transmission of meaningful information on multiple-driver signal lines is restricted to the assertion of high to low signal voltage transitions. By asserting meaningful information only on high to low transitions, the clock period for the bus may be set based on the voltage settling time resulting from only high to low transitions rather than from arbitrary transitions. As a result, the transmission of meaningful signals are all within the limits of incident wave switching and a high overall information transmission rate is achieved.

Abstract: A system and method for efficiently utilizing the output devices of a computer system to perform output functions. The output devices are capable of bidirectional communication and are capable of generating information pertaining to static and dynamic attributes of the respective output devices. Responsive to the additional information pertaining to the static and dynamic attributes of the output devices, particular ones of the output devices are allocated to effectuate particular ones of the output functions.

Abstract: A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).

Abstract: An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal.

Abstract: A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies.

Abstract: Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine in the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of a eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handing routine if the semaphore indicates that an exception occurred when the speculative instruction was executed, and the predicate is true, which indicates that the speculative instruction was properly executed.

Abstract: A PCMCIA card having an FPGA based card controller that is programmed with FPGA programming data stored on a host computer through a standard PCMCIA bus.

Abstract: A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.

Abstract: A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch instruction is in, or if the target address is in the next or previous 2K-byte block. The upper portion of the target address, its block number, which corresponds to the starting address of a 2K block, is generated from the target finder simply by taking the upper portion or block number of the branch instruction and incrementing and decrementing it, and using the block encoding in the finder to select either the unmodified block number of the branch instruction, or the incremented or decremented block number of the branch instruction. The lower portion of the target address that was stored in the finder is concatenated with the selected block number to get the predicted target address.

Abstract: A store queue is provided that forms an interface between a primary bus and a secondary bus and which temporarily stores data to be written via a memory or I/O channel to a peripheral device. The store queue allows partial writes executed on the primary bus to be combined within a common word storage cell of an internal FIFO buffer regardless of whether the consecutive partial writes result in an invalid byte combination. If the data being transferred does not constitute an invalid byte combination, the store queue executes a single write cycle on the secondary bus. If the data contained by the word memory cell constitutes an invalid byte combination, the store queue executes two or more partial writes on the secondary bus to transfer the data in the order it was received. The store queue includes a byte order tracking circuit, such as an accumulation counter, for tracking the order in which the bytes are written from the primary bus.

Abstract: A method and apparatus for selecting instructions from a sequence of undifferentiated bytes of instruction data is described. A first plurality of sequential bytes of instruction data is selected from the sequence of undifferentiated bytes of instruction data. A second plurality of sequential bytes of instruction data beginning at any selected byte in the first plurality is selected from the first plurality of sequential bytes of instruction data. A third plurality of sequential bytes of instruction data beginning at any selected byte in the second plurality is selected from the second plurality of sequential bytes of instruction data. The second plurality of sequential bytes is of sufficient length to provide instruction data for at least two clock cycles.