Abstract: An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions.

Abstract: A system and method of synchronizing data transfers between two processors having different bus transactions by providing a buffer for storing the data and a control logic for dividing a concurrent address and data bus transactions into an address bus transaction followed by a data bus transaction. During a read operation, the requesting device is forced to wait for data availability before entering the data bus transaction. During a write operation, the data bus transaction is delayed by using a storage mechanism that effectively separates the address transaction from the data transaction. The present invention also provides direct memory access fly-by operations between an input/output device and a memory device. These operations are accomplished by isolating a secondary bus from the system bus and allowing the destination device to capture the requested data as soon as it is available on the system bus.

Abstract: A slot token protocol for establishing and terminating data-links over a serial bus shared by multiple devices with low overhead, no supporting hardware, a low collision rate, and fast collision resolution. Of the devices sharing the serial bus, one device is designated as the master device with the remaining devices being designated as slave devices. The master device is responsible for controlling allocation of the serial bus between each of the slave devices so that only one slave device controls the bus at a time. The master device achieves this by requiring slave devices to submit bus requests before the requesting slave device is allocated control over the serial bus. In addition, a busy bus line may be included to reduce the likelihood of a data collision on the serial bus by connecting the master an slave devices with a bus busy line and allowing a slave device to signal to the other slave devices over the bus busy line that it intends to transmit a bus request.

Abstract: The scan cycle in a programmable logic controller is constructed so as to allow the PLC users program to execute an instruction to assign a user program section to which the PLC system is to transfer control upon the occurance of an instruction-specified event. Also allowed is the de-assignment of a user program section from an instruction-specified event. Moreover, the interrupt may happen at any portion of the PLC scan cycle and not merely at compilation time. This thereby allows for dynamically presetting values of characters and the like as well as pipelining of interrupts in the PLC.

Abstract: A two domain network linking a first and second data processing system enables efficient data transfers between modules in the first system and modules in the second system through linkage by bus exchange modules having message queues and snoop-write address queues in each domain. Each system also allocates bus access using a selectively adjusting bus access priority arbitration logic unit. The Snoop-Write address queues in each bus exchange module can temporarily hold a sequence of Write OP addresses snooped from one domain for invalidation in another domain without requiring the bus exchange module to dominate its access priority over other requesting modules.

Abstract: Power is conserved in a computing system by detecting when a user's hands are not placed over a keyboard for the computing system. When it is detected that the user's hand are not placed over the keyboard power to a display for the computing system is reduced. For example, the hands are detected by generating and detecting ultrasound waves. In one embodiment of the present invention, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands block a portion of the ultrasound waves from being detected. In another embodiment, the ultrasound waves are generated and detected from positions on a case of the computing system so that when the user's hands are placed on the keyboard, the user's hands reflect a portion of the ultrasound waves so that the portion of the ultrasound waves are detected.

Abstract: A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder.

Abstract: A component card interconnect apparatus for coupling a component card to a computer system. A component card includes a first group of in-line pins with first power pins for conveying a first voltage and a second group of in-line pins with second power pins for conveying a second voltage. The second voltage is lower than the first voltage. Either the first or the second voltage is conveyed at one time.

Abstract: In a data processing system, a first system processor is coupled to a first system bus. The first system processor includes a first bus controller. A second system processor having a second bus controller is coupled to a second system bus. The first bus controller is then coupled to a management bus, and the second bus controller is coupled to the same management bus. Thereafter, at least one feature device is coupled to the first system bus, the second system bus, and the management bus. The feature device is also configured to communicate system processor communications with the first system processor via the first system bus. Next, a problem that affects system processor communications over the first system bus between the feature device and the first system processor is detected. In response to detecting such a communications problem, a command is sent to the feature device via the management bus.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems. In various embodiments, multimedia devices transmit addressing and control information for a multimedia bus transfer either over the PCI bus or using a separate serial control channel. The multimedia bus may also comprise separate multimedia channels for different data types. In various embodiments, methods transfer periodic multimedia data over the multimedia bus.

Abstract: A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus that interconnects the devices, by use of an arbiter. When a circuit in an electrical device needs to use the bus, the circuit drives a request signal active to an arbiter, for example, in the form of a programmable logic device, such as a Programmable Array Logic (PAL.TM.) device included in the electrical device. The arbiter in turn transmits the request signal to all other arbiters. Therefore, each arbiter receives and monitors request signals from all circuits. If only one request signal is active at a given time, all arbiters receive the active request signal and each arbiter drives an acknowledge signal active to the respective local circuit. The circuit that requested the shared resource then uses the resource.

Abstract: A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors the CPU bus cycles in order to shut off the clocking signals supplied to the cache SRAM memory blocks when the CPU is not accessing the cache memory, thereby reducing the power consumption of the high-power SRAM devices. The power conservation apparatus resumes standard synchronized clocking to the cache SRAM blocks when the CPU is performing a cache-hit memory access cycle for maximum cache access performance.

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system expansion bus implements a new mode of operation specifically for real-time transfers. A real time signal is used to indicate that the expansion bus should be placed in a special real time mode. When not in special real time mode, the expansion bus operates as usual. The real time mode is optimized for the transfer of high bandwidth real-time information. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract: An adapter for use in a computer system having an IDE interface controller and a plurality of drives. The adapter is connected to the IDE controller and the plurality of drives and monitors information transmitted between the IDE interface controller and the plurality of drives. The adapter determines whether each of the plurality of drives is serviceable and whether data on each of the plurality of drives are equal. Identical data is directed to each of the plurality of drives when data on each of the plurality of drives are equal. Data is prevented from being directed to at least one of the plurality of drives when data on each of the plurality of drives are not equal. One of the plurality of drives is selected as a drive from which to read data.

Abstract: A data transfer for high-speed data transfer between two memories comprises three buffers for temporarily storing data being transferred, a source side controller for switching the buffers and for transferring the data in terms of blocks in such a manner that the leading buffer coincides with the address boundary of the source memory, and a destination side controller for switching the buffers and for controlling the transfer of data in terms of blocks. By switching over the buffers one after another, the data transfer from the source memory to the data transfer apparatus and the data transfer from the data transfer apparatus to the destination memory can take place simultaneously.

Abstract: An ID portion indicating the corresponding relationship between the number of a record contained in an FBA block and the position of the record is provided at the beginning of the FBA block. When a seek command has been issued by a host apparatus in the CKD format, a device adapter obtains the FBA block number corresponding to the parameter value (CCHH) of a head positioning command and positions a head at the FBA block of this number. Next, the device adapter obtains the FBA block number corresponding to the parameter value (sector value) of a set-sector command, reads one CKD track of blocks from the FBA block designated by the FBA block number and develops these blocks in a cache memory. A channel adapter searches the cache memory for a commanded record by referring to the information in the ID portion.

Abstract: A symmetrical multiprocessing system is provided that includes a central interrupt control unit. The central interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt sources include a plurality of peripheral devices coupled to a first peripheral bus, such as a PCI bus. The interrupt sources also include devices coupled to a second peripheral bus, such as an ISA bus. The central interrupt control unit is operative in two modes. In a first mode, referred to as a pass through mode, interrupts from ISA peripheral devices are provided through an interrupt controller, such as cascaded type 8259 interrupt controllers, to the central interrupt control unit. The central interrupt control unit then passes the interrupt directly to a master processing unit. PCI interrupts are provided through a PCI mapper to other available interrupt inputs of the interrupt controller.

Abstract: A termination synthesis technique that automatically derives an optimum termination scheme for interconnects in electronic circuits. The termination synthesis technique uses an adaptive partitioning approach to divide a large circuit into separate clusters that can be independently terminated. The technique can thus automatically derive the optimum termination type and location for large and complex circuits.

Abstract: A routing mechanism includes two acyclic non-adaptive virtual channels having two types of virtual channel buffers to store packets along deterministic virtual paths between nodes in an n-dimensional networked system, and an adaptive virtual channel having a third type of virtual channel buffer to store the packets along non-deterministic virtual paths between the nodes. The packets are routed between the nodes along either selected portions of the deterministic virtual paths or selected portions of the non-deterministic virtual paths based on routing information such that a packet is never routed on a selected portion of one of the non-deterministic virtual paths unless the third type virtual channel buffer associated with the selected portion of the one non-deterministic virtual path has sufficient space available to store the entire packet.

Abstract: A method of prioritizing computer resource access requests to a shared computer resource, such as a video frame buffer, includes the steps of providing a number, n, of priority schemes in correspondence with a like number of potentially requesting entities, where n is an integer greater than one, and where each priority scheme designates relative priority of the potentially requesting entities with respect to one another. Thus, for each priority scheme there exists one corresponding potentially requesting entity, and a number, n-1, of noncorresponding potentially requesting entities. Next, one of the priority schemes is selected for use as a current priority scheme. A set of currently requesting entities is then determined from the number of potentially requesting entities, and the current priority scheme is used to select a highest priority requesting entity from the set of currently requesting entities.