Abstract: An electronic package comprises a chip disposed on the upper surface of a substrate. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring. The electronic package comprises at least a surface-mountable device connected across the ground ring and the power ring. The present invention is characterized in that the surface-mountable device has at least a bonding region formed on one end contact thereof for bonding to a bonding wire thereby allowing the chip to be electrically connected to the ground ring or power ring directly through the end contact of the surface-mountable device.

Abstract: Circuit and circuit carries include a dielectric substrate having a conductive layer mounted thereon. The conductive layer is patterned to define a plurality of spaced apart conductive elements. A static charge dissipative layer is in contact with and extending between at least two of the conductive elements. The static charge dissipative layer has a surface resistivity of between about 1×105 and about 1×1010 ohms/□. The static charge dissipative layer is made of a material selected from the group consisting of diamond-like carbon, silicon nitride, boron nitride, boron trifluoride, silicon carbide and silicon dioxide. Circuits and circuit carriers according to the present invention allow static charges to be controllably and reliably dissipated from a surface of the circuit or circuit carrier such that the potential for damage from static discharge to electrical components connected to the circuit is reduced.

Abstract: An improved printed circuit board assembly is disclosed. The printed circuit board assembly comprises a first plate, a second plate attachably coupled to the first plate, and at least one printed circuit board sandwiched between the first plate and the second plate, the at least one printed circuit board extending over the entire area of the first and second plate. By utilizing an assembly in accordance with the present invention, the available space on each of the plurality of printed circuit boards is maximized. By maximizing the available space, more electronic circuitry can be incorporated onto the board. Furthermore, the exterior spacer design together with interior spacer elements firmly secures each printed circuit board while maintaining a constant separation between each board.

Abstract: A semiconductor device includes a ball grid array substrate including an upper insulating layer of laminated insulating layers, an intermediate insulating layer, and a lower insulating layer of laminated insulating layers; lines on each top surface of the insulating layers included in the upper insulating layer, the intermediate insulating layer, and the lower insulating layer, respectively; and a semiconductor chip having electrodes connected to the lines, the semiconductor chip being connected with solder balls through via holes in each of the insulating layers, the solder balls being located on an outermost surface of the lower insulating layer.

Abstract: A circuit board assembly having integrated circuit packages vertically arranged three dimensionally is used to increase electronic component density without increasing the size of the circuit board. For a preferred embodiment of the circuit board assembly, the printed circuit board has at least one primary mounting pad array affixed thereto, each pad of the array having first and second portions. Each lead of a first integrated circuit package is conductively bonded to the first portion of a different mounting pad of said primary array. A package carrier having a plurality of carrier leads attached thereto and a secondary mounting pad array on an upper surface thereof, covers the first package. Each lead of the carrier is coupled to a different pad of the secondary array and is also conductively bonded to the second portion of a different mounting pad of the primary array. Each lead of a second integrated circuit package is conductively bonded to a different mounting pad of the secondary mounting pad array.

Abstract: An apparatus which aligns a ball grid array (BGA) device over a substrate. The apparatus preferably includes a cup-shaped member for cupping and holding the solder balls of the BGA device, and an elongate member attached to the cup-shaped member. The cup-shaped member is attached between the BGA device and the substrate at two or more different positions so that the solder balls of the BGA device become aligned over the terminals of the substrate by operation of gravity.

Abstract: An organic land grid array having multiple built up layers of metal sandwiching non-conductive layers, having a staggered pattern of degassing holes in the metal layers. The staggered pattern occurs in two substantially perpendicular directions. Traces between the metal layers have reduced impedance variation due to the degassing hole pattern.

Abstract: The present invention comprises a single-substrate multiple chip module (MCM) assembly. The MCM assembly includes a repair-package-site ready MCM board having a top surface and a bottom surface, the top surface further includes a plurality of chip connection trace lines include a chip-select line. The MCM assembly further includes a plurality of bare integrated circuit (IC) chips mounted directly on the top surface of the MCM board each chip connected to the plurality of chip connection trace lines on the top surface. The repair-package-site ready MCM board further includes at least a repair-package-site disposed on the bottom surface having a plurality of connection terminals arranged according to a standard repair packaged-chip footprint. Each of the connection terminals is connected to a via connector disposed in the MCM board for electrically connecting to the conductive trace lines on the top surface.

Abstract: Disclosed herein is a printed circuit board comprising a ground layer and a signal layer in which the characteristic impedance of a specific source line is made to be not less than three times as large as the impedance at an upper limit frequency at which the electromagnetic wave radiation of a specific capacitor may occur. In this printed circuit board, variation of a power source voltage and unnecessary electromagnetic wave radiation can be suppressed.

Abstract: A printed circuit board includes a plurality of dielectric substrates. Each of the dielectric substrates includes a first and a second surface and has a first conductive layer formed on the first surface of the respective dielectric substrate. A first pattern of lands is formed in the conductive layer of at least two of the dielectric substrates. The pattern of lands of each dielectric substrate is substantially the same. An opening is formed through each of the lands to expose the respective dielectric substrate. Each of the openings in a respective pattern of lands has a diameter different than at least a portion of the other openings in the same pattern. The plurality of dielectric substrates are laminated in stacked relationship.

Abstract: Lands (1) for bonding a flip chip (3) are provided in a surface layer of a printed board (5). A dummy pattern or ground pattern (2) for preventing waving is provided on a layer next to the surface layer. The interlaminar thickness is made uniform by the dummy pattern or ground pattern (2). Since the flip chip bonding lands are arranged substantially in a plane, the flip chip lands are supported by the dummy or ground pattern to prevent waving from occurring so that high bonding quality can be obtained. In contrast to an arrangement in which a dummy pattern is not provided partially in a portion where bonding becomes unstable, a dummy pattern or a ground pattern is provided in an area corresponding to the outer shape of a flip chip to thereby support all the bonding lands of the flip chip. The flip chip bonding lands are kept in a uniform plane to suppress waving of the printed board so that bonding can be effected surely.

Abstract: An assembly that has an insert that fits onto a back plate. The back plate receives a circuit board that covers at least a portion of the insert. A components attaches to the circuit board and to the insert. The insert is made out of a material having a thermal expansion coefficient that is close to the thermal expansion coefficient of the bottom surface of the component, which allows the component to be securely soldered to the insert and therefore to the assembly. Preferably the insert is also made out of a good conductor to provide a good electrical conduction path between the component and the ground plane of the circuit board that contact the insert. The insert either fits into a recessed area in the back plate or attaches to the top of the back plate. In an alternative embodiment, the assembly has a circuit board with a contact opening and a back plate with a raised area that fits into the contact opening. The contact opening exposes a portion of ground plane on the circuit board.

Abstract: A flexible circuit board and a method for making a flexible circuit board. The flexible circuit board (10) is formed from a substantially rigid material and includes a first portion (12) and a second portion (14) coupled by a bend region (16). The bend region (16) includes at least one bend (40, 52) having a radius less than 120 mils.

Abstract: A module, such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprise a pattern of metal contacts having a first and a second surface and electrically-conductive vias built up on the first surface of the metal contacts. A layer of dielectric adhesive on the first surface of the pattern of metal contacts surrounds the electrically-conductive vias except the ends thereof distal from the metal contacts. An electronic device has electrical contacts connected to the exposed ends of the conductive vias, as by wire bonds or by flip-chip type connections.

Abstract: A high density integrated circuit module having complex electrical interconnection is described, which includes a plurality of stacked level-one integrated circuit devices, wherein each level-one device includes an integrated circuit die and a plurality of electrical leads extending from the die; and a plurality of non-linear rails adapted to electrically and thermally interconnect selected leads of selected stacked level-one devices within the module, wherein at least some of the plurality of non-linear rail include a lead interconnect portion which is adapted to at most partially surround and receive a selected lead from one of the stacked level-one devices. Other embodiments include TSOP modules having leads reduced in width to allow additional selected non-linear rails to interconnect with select leads in the module. Strain relief for the rail/circuit board substrate connection in harsh environment applications is also provided.

Abstract: An integrated circuit package pin indicator that may include probe guides. The indicator includes a top marking plate with indicia for the multiple pins of the IC package. The top plate has individual indicia for each pin, and will have numerical or alpha labels for some or all of the pins, depending on the number of pins present. The top marking plate may include a securing means to attach the top marking plate to the top of the IC package and to hold the top marking plate in place. Each pin marker terminates in a hole or slot that is adapted to guide a probe to a selected pin. The pin indicator can be used with both through hole and surface mount IC boards.

Abstract: A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.

Abstract: According to the invention, a multilayered image sensor is backmounted to a plate, and the plate in turn, is installed in a holding pocket of a device. In that the scheme takes advantage of a high controllability of a mounting plate's thickness, the mounting scheme provides for tight control of holding forces with which an image sensor is secured in an imaging device. In that the scheme provides for back mounting of image sensor on a planar surface, the mounting system provides tight control of an imaging assembly's pixel plane to fixed point in space distance.

Abstract: A retainer adapted to mount an electronic device to a circuit board, includes two spaced arms, each having an elongate body defining a channel for receiving an edge of the device thereby retaining the device between the two arms. Each retaining arm defines two cavities therein respectively proximate opposite ends of the body. Each cavity has a square configuration to snugly receive a square nut therein. The cavity has a bottom periphery to support the nut and a top periphery to retain the nut in the cavity. A through hole is defined in the bottom periphery to receive a bolt that extends from the circuit board and threadingly engages with the nut thereby securing the retaining arm to the circuit board. The top periphery of the cavity defines a circular recess and a cylindrical section of the nut is received and retained in the recess for further securing the nut in the cavity.

Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.