Patents Examined by John B. Vigushin
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Patent number: 6535398Abstract: Modularly constructed multichip modules with are disclosed. A plurality of miniature capacitor substrates and/or miniature resistor substrates are assembled and attached to a base substrate, preferably in a regular pattern. Power supply substrates are preferably attached to the base substrate along with the miniature substrates. All of the attached components are preferably pretested and have thicknesses close to one another. The pretesting substantially increases the manufacturing yield. Gaps between the miniature substrates and power supply substrates are filled with a polymer material, such as a powder-filled polyimide precursor. Thereafter, dielectric layer is formed over the components to provide a more planar surface. The dielectric layer is preferably planarized, such as by a chemical mechanical polishing process, to provide for a more planar layer.Type: GrantFiled: March 7, 2000Date of Patent: March 18, 2003Assignee: Fujitsu LimitedInventor: Larry L. Moresco
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Patent number: 6535397Abstract: An interconnect structure interconnects electronic modules and includes a backplane assembly formed from a substantially rigid backplane plate that carries RF connectors and a digital motherboard having digital connectors for mating with digital connectors of electronic modules. A controlled impedance interconnect circuit is positioned on the rear surface of the backplane plate and interconnects the RF connectors carried by the backplane plate and digital connectors of the digital motherboard. A rack receives the backplane assembly and supports a plurality of electronic modules that are interconnected to each other via the backplane assembly.Type: GrantFiled: May 31, 2001Date of Patent: March 18, 2003Assignee: Harris CorporationInventors: William Clark, Douglas Heckaman, Edward Bajgrowicz
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Patent number: 6534725Abstract: A high-frequency switch includes: a high-frequency circuit board including an MIC substrate, a microstrip line disposed on a front surface of the MIC substrate, and a signal wiring layer and a front surface grounding conductor disposed along the microstrip line; bumps disposed on the microstrip line, the signal wiring layer, and the front surface grounding conductor; and a semiconductor chip disposed on the high-frequency circuit board through the bumps. A gate electrode of a transistor of the semiconductor chip is connected to the signal wiring layer of the high-frequency circuit board through at least one of the bumps; a source electrode is connected to the front surface grounding conductor through at least one of the bumps; and a drain electrode is connected to the microstrip line through at least one of the bumps.Type: GrantFiled: June 5, 2001Date of Patent: March 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshihiro Tsukahara
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Patent number: 6535395Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.Type: GrantFiled: December 3, 2001Date of Patent: March 18, 2003Assignee: Intel CorporationInventors: Joe A. Harrison, Edward R. Stanford, Thomas G. Ruttan
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Patent number: 6531763Abstract: Interposers having an encapsulant fill control feature are disclosed. In one embodiment, an interposer includes a substrate having a first surface proximate the semiconductor component, and a fill control feature projecting from the first surface toward a region adapted to be occupied by a semiconductor component. The fill control feature is positioned between the region and the substrate and is sized to at least partially block an opening between a semiconductor component that may be positioned in the region and the first surface. As an encapsulant material is flowed about the semiconductor component, the fill control feature at least partially blocks the encapsulant material from entering the opening. The encapsulant material may then substantially surround the semiconductor component, after which the encapsulant material may substantially fill a space between the semiconductor component and the interposer.Type: GrantFiled: August 15, 2000Date of Patent: March 11, 2003Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, David J. Corisis
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Patent number: 6528889Abstract: An electronic circuit device has an insulating substrate and an integrated circuit having a surface disposed opposite to and confronting a surface of the insulating substrate to form a gap therebetween. An adhesive material is disposed in the gap between the insulating substrate and the integrated circuit. Bumps project from the surface of the integrated circuit towards the surface of the insulating substrate. Electrode patterns are electrically connected to the bumps to electrically connect the integrated circuit to the electrode patterns. An adhesion-reinforcing pattern is spaced-apart from and surrounded by the electrode patterns. The adhesion-reinforcing pattern is disposed on a portion of the surface of the insulating substrate confronting a portion of the surface of the integrated circuit from which the bumps do not project.Type: GrantFiled: June 29, 1999Date of Patent: March 4, 2003Assignee: Seiko Instruments Inc.Inventors: Tsutomu Matsuhira, Atsushi Endo
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Patent number: 6528732Abstract: A circuit device board having a desired characteristic is provided by bonding dielectric substrates. A printed board 11 carrying patterns 11a and 11b incorporating a resonator is joined by a prepreg 13 to a printed board 12 carrying patterns 12a and 12b, which are substantially identical to the patterns 11a and 11b, so that the patterns come opposite to each other. As a grounding conductor is provided on the outer side of each of the printed boards 11 and 12, a band-pass filter having the three-plate structure is completed. The patterns 11a and 12a are connected to each other for determining the signal input while the patterns 11b and 12b are connected to each other for determining the signal output. Accordingly, the frequency response can be obtained at a desired level regardless of the thickness of the prepreg 13.Type: GrantFiled: August 18, 2000Date of Patent: March 4, 2003Assignee: Sony CorporationInventors: Akihiko Okubora, Takayuki Hirabayashi, Hideyuki Shikichi
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Patent number: 6514777Abstract: An improved bonding strip for a printed circuit to facilitate quality inspection. The bonding strip has functional regions and non-functional regions. A functional region is indicated by an area of the bonding strip having a first dimension in width. A non-functional region is indicated by an area of the bonding strip having a second dimension in width. The first dimension may be either wider or narrower than the second dimension.Type: GrantFiled: January 10, 2001Date of Patent: February 4, 2003Assignee: International Business Machines CorporationInventors: Marshall L. Brown, James A. Busby, Raymond A. Phillips, Jr., John A. Potenza, Jirina D. Shupp, J. Robert Young
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Patent number: 6515865Abstract: An improved and low cost electrical connection for use in circuit boards for key fobs incorporates a plurality of generally cylindrical pin members which are symmetric about a central axis. The use of the symmetric pin allows automatic insertion of the pin in that the orientation of the pin relative to the board is unimportant. The pin has a generally tapered transition portion which provides a contact surface for the battery, and this transition portion is also symmetric such that the orientation of the pin relative to the board is unimportant. Further, a stop face on the pin provides a stop for insertion of the pin into the circuit board such that the pin is at the desired height relative to the battery and such that the transition portion will provide electrical contact to the battery.Type: GrantFiled: May 29, 2001Date of Patent: February 4, 2003Assignee: Siemens VDO Automotive CorporationInventors: Susan Johnson, Tejas B. Desai, Kyle Cleland
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Patent number: 6507498Abstract: The invention relates to a multiple-component unit in which at least two passive components have been realized one above the other. A multiple-component unit thus comprises at least one resistor and at least one capacitor, or at least two capacitors. This space-saving construction allows for a miniaturization of circuits. A further miniaturization can be achieved in that the multiple-component units are not manufactured as discrete components, but are integrated into ICs.Type: GrantFiled: January 26, 2000Date of Patent: January 14, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Mareike K. Klee, Hans P. Lobl, Rainer Kiewitt, Paul H. P. Van Oppen, Robert J. A. Derksen, Hans-Wolfgang Brand
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Patent number: 6507497Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.Type: GrantFiled: May 4, 2001Date of Patent: January 14, 2003Assignee: Shinko Electric Industries, Co., Ltd.Inventor: Naohiro Mashino
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Patent number: 6504724Abstract: A first casing (11, 12)includes a first end (30, 31). A second casing (11, 12) is mated with the first casing (11, 12). The second casing (11, 12) includes a second end (30, 31) facing the first end (30, 31). A flexible circuit member (23) is housed between the first and second casings (11, 12). The circuit member (23) is drawn out from the first and second ends (30, 31). The circuit member (23) is retained between the first and second ends (30, 31) under pressure.Type: GrantFiled: October 29, 2001Date of Patent: January 7, 2003Assignee: Yazaki CorporationInventors: Yasuyoshi Serizawa, Takahiko Suzuki, Minoru Kubota, Kenji Iwasaki
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Patent number: 6504107Abstract: An assembly unit comprises a printed circuit board (10) and an optical component (54, 56, 58), the printed circuit board (10) being provided with at least one electro-optical component (16), at least one conducting track (24) for the connection of the electro-optical component (16), as well as a three-dimensional, microstructured adjustment formation (12), the electro-optical component (16) being precisely arranged relative to the latter, and a three-dimensional positioning formation (52) being provided on the optical component (54, 56, 58) and cooperating with the adjustment formation (12) of the printed circuit board (10) in such a way that the optical component (54, 56 58) is precisely coupled with the electro-optical component (16) of the printed circuit board (10).Type: GrantFiled: July 23, 2001Date of Patent: January 7, 2003Assignee: Harting Elektro-optische Bauteile GmbH & Co. KGInventor: Hans Kragl
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Patent number: 6501664Abstract: A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e.g., a motherboard), with a surface-mounted electrical component (e.g., a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.Type: GrantFiled: June 30, 2000Date of Patent: December 31, 2002Assignee: Intel CorporationInventor: Jeffrey L. Krieger
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Patent number: 6501663Abstract: A three-dimensional interconnect system is disclosed. The interconnect system electrically connects electrical devices that are disposed on different physical planes. The interconnect system includes a plurality of contiguously interconnected electrically conductive droplets such as solder ball droplets produced by a print-on-demand solder jet system. An interconnect is formed by repeatedly ejecting the conductive droplets along a predetermined path between components to be connected. Each ejected droplet is disposed adjacent to another ejected droplet to form a contiguously linked chain of droplets that bridge a physical gap between the components. A non-conductive coating can be deposited on the interconnect to protect the interconnect from damage and to encase the interconnect. The electrical resistance of the interconnect can be reduced by reflowing the droplets that form the interconnect, whereby the coating that encses the interconnect is operative to maintain the shape of the interconnect after reflow.Type: GrantFiled: February 28, 2000Date of Patent: December 31, 2002Assignee: Hewlett Packard CompanyInventor: Alfred I-Tsung Pan
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Patent number: 6498308Abstract: A semiconductor module includes a chip formed with an integrated circuit, a first external connecting terminal electrically connected to the integrated circuit, a printed wiring board having a second external connecting terminal, and a conductive material electrically connecting the first external connecting terminal with the second external connecting terminal, wherein the conductive material is formed so as to cover a sidewall of the second external connecting terminal. Accordingly, a semiconductor module is provided that can avoid an inferior connection caused by a crack between the lead and the pad.Type: GrantFiled: March 10, 2000Date of Patent: December 24, 2002Assignee: Oki Electric Industry Co., Ltd.Inventor: Akira Sakamoto
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Patent number: 6495768Abstract: A tape carrier package that is capable of preventing a short between adjacent pads in boning the tape carrier package mounted with an integrated circuit onto a liquid crystal panel and a print wiring substrate. In the package, a base film is mounted with an integrated circuit. Input pads are connected to the integrated circuit to input an external input signal to the integrated circuit. Each of output pads has a first portion extended to the integrated circuit, and a second portion extended to the first portion to have a narrower line width than the first portion.Type: GrantFiled: July 20, 2000Date of Patent: December 17, 2002Assignee: LG. Philips LCD Co., LTDInventor: Hyoung Soo Cho
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Patent number: 6496377Abstract: A vehicle electric power distribution apparatus is provided which includes a plurality of vertically stacked conductive circuit layers, each layer including an array of contact pads, a layer of electrically insulating plastic material between each of the conductive circuit layers, at least some of the contact pads are electrically connected to selected other contact pads of the same conductive circuit layer via integrally formed conductive traces. In addition to the stacked circuit layers the apparatus includes a plurality of conductive pins providing electrical contact between selected contact pads of different selected conductive circuit layers.Type: GrantFiled: October 9, 1996Date of Patent: December 17, 2002Assignee: CooperTechnologies CompanyInventors: Lawrence R. Happ, Jacek Korczynski, Willaim R. Bailey, Alan Lesesky
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Patent number: 6496382Abstract: A radio frequency identification tag is made with printed antenna coil integrated on a flexible substrate, and an integrated circuit area of the substrate adjacent the antenna coil for carrying circuit elements. The radio frequency identification tag is designed to be sufficiently robust to withstand the rigors of mail efficiency processing measurement applications.Type: GrantFiled: October 25, 2000Date of Patent: December 17, 2002Assignee: Kasten Chase Applied Research LimitedInventors: Donald Harold Ferguson, Mircea Paun
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Patent number: 6496384Abstract: A circuit board assembly and method of fabricating an assembly are provided. The assembly preferably comprises a first circuit board defining an aperture and a second circuit board having an edge. The first circuit board has at least one conductive feature proximate the aperture, and the second circuit board has at least one conductive feature proximate the edge. Each board has at least one circuit trace in electrical communication with its respective conductive feature. The conductive features of the boards are placed in electrical communication with each other by way of the edge of the second board being disposed in the aperture of the first board. A solder joint can be disposed on the assembly so as to connect the first and second boards.Type: GrantFiled: September 21, 2001Date of Patent: December 17, 2002Assignee: Visteon Global Technologies, Inc.Inventors: Jorge Morales, Cesar Avitia