Abstract: A PCB assembly which allows economical and reliable rework. The PCB assembly contains a soldermask and a trace with a portion of the trace exposed by a soldermask relief. When one needs to rework the PCB assembly, one bonds a rework wire, using conventional intermetalic bonding materials, to the portion of the trace exposed by the soldermask relief. There is no need to bond a rework wire to a component. Further, there is no need to scrape off the soldermask and possibly damage the traces and/or vias. The bonds are high reliability bonds, and the labor required to perform such bonds are minimal.

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Abstract: An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.

Abstract: A substrate structure for an integrated circuit package. The substrate is electrically connected to a circuit board and an integrated circuit. The substrate includes a plurality of metal sheets and glue. The metal sheets are arranged opposite to each other. Each of the metal sheets includes a first surface and a second surface. The glue is used for sealing the plurality of metal sheet to form the substrate. The first surfaces and second surfaces of the metal sheets are exposed to the outside of the glue so as to form a plurality of signal input terminals for electrically connecting to the integrated circuit and a plurality of signal output terminals for electrically connecting to the circuit board. Thus, the signal output terminals of the metal sheets can be electrically connected to the circuit board smoothly. Furthermore, the signal transmission distance between the integrated circuit and the circuit board can be shortened so that better signal transmission effect can be obtained.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A technique for improving electrical signal performance in multilayer circuit boards by eliminating the need for electrically conductive vias is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board having an electrically conductive signal layer disposed beneath at least one dielectric layer. The improvement comprises a cavity in the multilayer circuit board extending through the at least one dielectric layer so as to expose at least a portion of the electrically conductive signal layer within the cavity. The cavity is sized to accommodate an electronic component therein such that the electronic component makes electrical contact with the exposed portion of the electrically conductive signal layer, thereby eliminating the need for an electrically conductive via electrically connected to the electrically conductive signal layer and formed through the at least one dielectric layer or any other layer of the multilayer circuit board.

Abstract: A printed circuit board and a pad apparatus having a solder deposit formed on the pad apparatus by using a mask having a slit are provided. The slit has the same shape as the solder deposit. The solder deposit includes first and second end portions individually shaped and sized to completely cover at an end portion of the pad a predetermined area of an end portion of the pad, the area defined by both the entire width of the pad and a predetermined length from the end of the pad. A connection web extends between the two end portions to integrate the two end portions into a single structure and is a longitudinal part having a width smaller than any one of both the width of the pad and the width of each of the two end portions. First and second trapezoidal portions are respectively formed at junctions between opposite ends of said connection web and one of the two end portions. The mask has a slit formed at a position corresponding to the position of the solder deposit.

Abstract: The invention relates to a method for the verification of the presence and proper orientation of a component on a printed circuit board. The board has a plurality of areas for receiving a component respectively. Each area is marked in the center thereof with a first marker. Adjacent each area, and indicative of the polarity of the component, a second marker is marked on the board. The presence or absence of a component can be evaluated by inspecting the board after it has been populated and determining whether any of the first markers appear, indicating that a component is missing. Verification of the polarity of a component is done by placing a marker on a portion of a component required to be installed in a predetermined position indicative of polarity. Inspection of the board once it has been populated will determine if the component is in the proper orientation by verifying if the second marker and the marker on the component are in alignment.

Abstract: A cage for an electronic component includes two spaced apart cast walls, and a roof member and a floor member connected to the two spaced apart cast walls. The walls are substantially identical, and the roof member and the floor member are each formed of a damped metallic laminate panel.

Abstract: A scalable electronic system is disclosed, comprised of multiple modular electronics clusters. Each modular electronics cluster comprises a receptacle for routing signals, and multiple resource cartridges for performing electronic functions. The resource cartridges are capable of being aligned in close proximity to the receptacle for communicating signals to and from the receptacle. In addition, the resource cartridges aligned with the receptacle are also capable of communicating with each other. The resource cartridges can be aligned or removed from alignment with the receptacle, without the need for additional electrical connection hardware. The receptacle includes at least one vertical transport channel for communicating with other modular electronics clusters.

Abstract: A new packaging technology which improves the electrical and mechanical performance of the circuits using magnetic elements. High frequency current loops generate electromagnetic fields which are radiated or induce high frequency current in the rest of the circuit. To reduce the radiated field, these loops have been minimized by locating the high frequency switching components close to each other and very close to the magnetic elements. By separating the high frequency switching electronic components from the rest of the electronic components and locating them on the same multilayer PCB where the magnetic element is constructed, optimal results are obtained.

Abstract: A semiconductor card includes a printed circuit substrate and one or more semiconductor components, such as dice or packages, mounted to the substrate. The substrate is initially a segment of a strip containing several substrates. The substrate is defined by a peripheral opening in the strip, and is connected to the strip by connecting segments. The card also includes a plastic body molded to the substrate and having notches that initially align with the connecting segments. The notches provide access for severing the connecting segments, and also enclose any slivers of substrate material resulting from severing of the connecting segments. A method for fabricating the package includes the steps of providing the strip, and providing a molding apparatus configured to mold the plastic body to the substrate. The molding apparatus includes pins configured to contact the connecting segments to form the notches.

Abstract: An integrated circuit package includes at least one one-time programmable element, such as a fuse, having a first end and a second end separated by a programmable link. The programmable element is positioned on a surface other than the top surface, e.g., a side surface or the bottom surface of the package substrate to render them less conspicuous to unscrupulous suppliers intent on tampering with the package. The information programmed by the fuses may relate to speed or voltage ratings for a microprocessor.

Abstract: A semiconductor device-mounting construction including a semiconductor device having a plurality of electrodes formed on one main surface thereof. A printed circuit board having a writing pattern formed on one main surface thereof and a plurality of solder bumps interposed between the plurality of electrodes and the writing pattern to electrically connect the semiconductor device and the printed circuit board together. All of the voids, which are present in an interface of each of those of the plurality of solder bumps which are disposed closest to an outer peripheral edge of the semiconductor device, joined to the semiconductor device, are fine, and generally uniform in size.

Abstract: A lower semiconductor element is mounted facing down on an insulating circuit board, and an upper semiconductor element is stacked facing up on the lower semiconductor element. Openings are provided in the insulating circuit board at a location facing the element electrodes of the lower semiconductor element, and the element electrodes of the lower semiconductor element are connected to the board electrodes on the lower surface of the insulating circuit board through the openings. Also, the element electrodes of the upper semiconductor element are connected to the board electrodes on the upper surface of the insulating circuit board. Thus, a high-density semiconductor device is provided by stacking a plurality of semiconductor elements.

Abstract: A technique for increasing electronic component density on multilayer printed circuit boards is disclosed. In one embodiment, the technique is realized as an improved multilayer circuit board for enabling the stacking of electronic components. The multilayer circuit board has a first electrically conductive layer and a second electrically conductive layer separated by at least one dielectric layer. The improvement comprises a cavity in the multilayer circuit board extending through the first electrically conductive layer and the at least one dielectric layer so as to expose at least a portion of the second electrically conductive layer within the cavity.

Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.

Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Abstract: A semiconductor device in a chip size package form having a high durability and reliability and realizing a small size with high density, and an electronic apparatus mounting the same, connected to a motherboard by soldering, comprising a semiconductor chip wherein bumps are formed on pad portions thereof; an interposer supporting the bumps mechanically and having through-holes wherein conductors are formed and connected to the bumps electrically; and a sealing resin buried between the semiconductor chip and the interposer, wherein the interposer is formed from a material having a higher glass transition temperature than a curing temperature of the sealing resin, a coefficient of linear expansion of the interposer is of a value substantially intermediate between that of the motherboard and that of the semiconductor chip, and/or the interposer is formed from a material having a bending strength of 400 MPa or more.

Abstract: Surface mount device packages with increased mounting strength and a method therefor. In one embodiment, an, electronic device is made up of a device package and one or more electrically conductive terminals. For surface mounting, the device terminals are each provided with a mounting surface which is bonded using a conductive adhesive to a corresponding contact pad on a circuit board. The terminals are further provided with at least one groove across the mounting surface. When conductive adhesive is used to mount the device on a circuit board, this groove serves to form the conductive adhesive into a ridge or “dam” over the contact pad. This provides increased mounting strength which may eliminate the need for additional adhesive material to provide side reinforcement of the device, and thereby allow an increase in the packing density of devices on the circuit board.