Abstract: A method and embedded bus bar structure are provided for implementing power distribution in an electronic system. A stiffener includes an embedded power bus bar structure for distributing power. The embedded power bus bar structure has a predefined pattern within a selected area of the stiffener. The selected area is separated from at least one predefined area. A printed circuit board is mounted to the stiffener and electrically connected to the embedded power bus bar structure. The embedded power bus bar structure can include multiple spaced apart power bus bars, enabling the power distribution of multiple voltage levels. The predefined pattern of the embedded power bus bar structure within the selected area of the stiffener is separated from each predefined site for a Land Grid Array (LGA).

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.

Abstract: A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.

Abstract: A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

Abstract: A method and apparatus for decreasing crosstalk between conductors, particularly differential pairs, that are routed in high-density patterns on printed circuit boards system. In one embodiment of the invention, a single-ended conductor is divided at a first point into two single-ended conductors of equal width, with the two single-ended conductors being routed around and alongside a differential pair of conductors. Equal and opposite noise is coupled onto each branch of the single-ended signal from each side of the differential pair. The two single-ended conductors are rejoined at a second point to form a combined single-ended conductor. Signals traveling along the two separate paths of the single-ended are combined at the second point and noise carried in the respective signals is cancelled. Noise coupled into the differential pair from the two single-ended paths is eliminated at the receiving end as common mode noise.

Abstract: A wiring board is arranged on the back side of a tape carrier package (TCP), the upper edge of a notch in the leftmost TCP and an outer edge of a branch of the leftmost terminal of the leftmost output terminal portion of the wiring board are arranged on the same plane, the lower edge and the outer edge of the branch are arranged on the same plane, and a terminal and the corresponding terminal of the output terminal portion are superposed on each other without a shift therebetween. Similarly, the upper end of a notch in the rightmost TCP and an outer edge of a branch of the rightmost terminal of the rightmost output terminal portion are arranged on the same plane, the lower edge and the outer edge of the branch are arranged on the same plane, and a terminal and the corresponding terminal of the output terminal portion are superposed on each other without a shift.

Abstract: An electronic device having a first semiconductor device for powering MOSFET and a second semiconductor device for controlling on a principal surface and sealed by a resin body. The first semiconductor device has a semiconductor chip with a first and a second electrodes formed on a first principal surface and also with a third electrode formed on a second principal surface, and an insulative or dielectric sheet laid out between a first lead and the first principal surface of the semiconductor chip and between a second lead and the semiconductor ship for covering a specified area of the first principal surface of the semiconductor chip other than a region in which a plurality of projected electrodes are disposed. An upper surface of the first and second leads of the first semiconductor device is positioned under an upper surface of the resin body of the second semiconductor device in a thickness direction of a wiring substrate.

Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract: A flexible printed wiring board is provided, including a flexible electrically insulating polyimide substrate, first and second electrically conductive patterns each including conductive strips arranged in parallel with each other on opposed major surfaces, respectively, of the electrically insulating substrate, and first and second flexible electrically insulating polyimide covers cemented to the respective major surfaces of the electrically insulating substrate by first and second electrically insulating adhesive layers by thermocompression bonding such that the first and second conductive patterns are covered with the first and second flexible electrically insulating covers, respectively.

Abstract: A semiconductor package includes a chip carrier to receive a semiconductor with a dimension generally greater than 26 mm. The chip carrier has a first coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the semiconductor. A stress inhibiting intermediate mounting substrate is connected to the chip carrier through a first array of solder connections. The stress inhibiting intermediate mounting substrate has a second coefficient of thermal expansion that is larger than the coefficient of thermal expansion of the chip carrier and smaller than or equal to the coefficient of thermal expansion of the printed circuit board. Alternate preferred inventive embodiments allow for the cleaning and removal of residual flux and other debris in packaging.

Abstract: The present invention discloses an improved transistor with a &pgr;-gate structure usable at microwave and millimeter wave and comprises a GaAs wafer, GND formed on the bottom surface of the wafer and grounded to source layers formed on the top surface of the wafer by the process of back-side via-hole. A drain is formed on the top surface of the wafer between the source layers and has an air layer on top. A gate, shaped as a result of using an air bridge technique, contacts the top surface of the wafer between the source layers and the drain so as to support the wafer at laterally opposite ends over the air layer of the drain. The gate having &pgr;-structure improves noise characteristics of the transistor because of low electrical resistance, which is a result of the gate structure straddling above the drain stage.

Abstract: A memory device is constructed by connecting a plurality of flat high-speed memory modules each including a connector on one side of which input side and output side terminals for dealing with a high-speed signal of plural-bit width whose impedance is controlled and which is transmitted from a memory controller to a terminal resistor are arranged. The memory device in which memory modules can be cascade-connected and which can maintain the impedance of a memory bus signal in a constant value by use of an inexpensive multi-layered circuit board structure is provided. A socket mounting structure of the memory device and a mounting method of the memory device is provided.

Abstract: A resin-formed substrate is provided which has a component side for mounting an electronic component thereon, and a solder side for soldering thereto a lead extending from the electronic component, which is the reverse to the component side, the resin-formed substrate comprising a metal frame forming an electronic circuit pattern; and a resin covering the metal frame, the resin having an aperture formed therein, for exposing a portion of the metal frame, wherein the portion of the metal frame exposed through the aperture serves as an electrode portion for mounting of the electronic component, wherein the resin has a rib integrally formed on the component side, thereby suppressing warp of the resin-formed substrate due to a temperature difference made between a component side and a solder side during soldering.

Abstract: An wiring board is provided so as to wrap a semiconductor chip, and on the outer surface of wiring board, a plurality of external terminals are provided three-dimensionally, i.e., on the upper, lateral and bottom sides. External terminals are connected to an electrode area of the wiring pattern provided to wiring board for electrically connecting to an external element. According to this configuration, a structure of an electronic element enabling free arrangement of an electronic device addressing various designs of the final products, and an electronic device using the electronic element can be provided.

Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.

Abstract: Apparatus is described for capacitively signalling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signalling, and reduces or eliminates the requirements for exotic metallurgy.

Abstract: Provided is a heat sink designed to constrain warpage during thermal cycling. The heat sink is composed of a picture frame stiffener and a heat spreader lid. The stiffener has a thickness greater than that of the height of a die bonded on a substrate in the package which the heat sink is or is to be used. The increased thickness of the stiffener beyond conventional designs serves to increase its stiffness and thereby enhance its capacity to constrain the substrate to prevent its warpage during thermal cycling. The thickened stiffener is coupled with an elevated heat spreader lid, that is, a heat spreader lid with a elevated central portion configured for engagement with the picture frame stiffener such that a central portion of at least one side of the heat spreader lid extends into the opening in the picture frame stiffener. As a result, the heat spreader lid is in a position to constrain warpage of the package by applying a counter force against a warping die.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: A plug-in type electronic control unit is comprised of a wiring board, a plurality of electronic parts mounted on one surface of the wiring board by utilizing a wireless bonding process, and a plug member mounted on the other surface of the wiring board by utilizing a wireless bonding process. It is possible to suppress the planar extent of the unit by such a laminated structure, and to suppress the extent of the unit in a laminating direction by the employment of the wireless bonding process. Thus, it is possible to achieve a reduction in size of the plug-in type electronic control unit.