Patents Examined by John D. Smith
  • Patent number: 4695479
    Abstract: A method of forming a gate insulating film on a MOSFET. After a SiO.sub.2 film is formed by thermal oxidation as a gate insulating film on a MOSFET, the SiO.sub.2 film is removed by selective etching from the surface area other than the MOSFET region, and an oxygen doped semi-insulating polycrystalline silicon film is depostied thereon. Then, a silicon nitride layer is deposited and a SiO.sub.2 film is formed by CVD method on the surface area other than the MOSFET region.
    Type: Grant
    Filed: March 12, 1986
    Date of Patent: September 22, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukinori Nakakura, Nobuyuki Kato
  • Patent number: 4695481
    Abstract: A method and device of performing plating of an item having a row of fine parts, e.g. a flatpack IC are disclosed. The method comprises immersing said item in a bath of molten solder, removing said item from said bath while maintaining said item in an attitude such that said row of fine parts is sloped with respect to the surface of said molten solder, and causing flux to exert a fluxing action on said molten solder which adheres to said fine parts, thereby decreasing the surface tension of the solder adhering to said fine parts and preventing bridges of solder from forming between said fine parts.
    Type: Grant
    Filed: March 27, 1986
    Date of Patent: September 22, 1987
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Yuuji Kawamata, Tomohiko Iino, Ryoichi Suzuki, Noriyuki Haga
  • Patent number: 4695482
    Abstract: Method and apparatus for applying a flow of insulating material such as silicone to predetermined locations on printed circuit boards to avoid damaging the components on the circuit boards, such as solenoids and buzzers, whose functions will be impaired by the application of such material thereto. The apparatus is comprised of a pump which delivers a flow of insulating material to a manifold, the manifold having a plurality of lengths of flexible tubing attached thereto which serve as nozzles for dispensing the flow of insulating material. A printed circuit board is mounted on a conveyor and the conveyor is advanced until the printed circuit board is under the manifold, at which time the manifold is lowered to place the nozzles in close proximity to the printed circuit board so that the flow of insulating material will be directed to predetermined locations on the printed circuit board. The flexible nozzles are selectively positioned to direct the flow to those predetermined locations.
    Type: Grant
    Filed: January 21, 1986
    Date of Patent: September 22, 1987
    Inventor: Klaus D. Weiswurm
  • Patent number: 4693907
    Abstract: A printed circuit board having a multi-layered copper plating film with excellent mechanical characteristics is obtained by a process of non-electrolytic copper plating comprising at least one sequence of the following steps (a)-(d):(a) immersing the printed circuit board to be plated in a non-electrolytic copper plating bath;(b) drawing out the immersed board from the bath;(c) immersing the drawn out board in the bath; and(d) drawing out the immersed board from the bath.In place of using one non-electrolytic copper plating bath, two non-electrolytic copper plating baths containing same solutes and having different concentration of the solutes in baths and/or different temperature of the baths respectively are used alternately.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: September 15, 1987
    Assignee: Ibiden Kabushiki Kaisha
    Inventor: Takakazu Ishikawa
  • Patent number: 4693207
    Abstract: An apparatus for the growth of semiconductor crystals in which the surface of a substrate is irradiated with molecular beam containing elements by which semiconductor thin films are formed on the substrate within a molecular beam epitaxial growth chamber in a high vacuum, thereby achieving molecular beam epitaxial growth of semiconductor thin films onto the substrate, wherein said molecular beam epitaxial growth chamber comprises an optical window through which light is introduced into said growth chamber and irradiates the surface of said substrate during molecular beam epitaxial growth.
    Type: Grant
    Filed: December 6, 1985
    Date of Patent: September 15, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiro Hayakawa, Takahiro Suyama, Kohsei Takahashi, Saburo Yamamoto
  • Patent number: 4692346
    Abstract: A method and apparatus for controlling surface chemistry on objects plated in an electroless plating bath. Cyclic voltammetry measurements are made for different pH conditions of the bath. Pourbaix diagrams are determined from these measurements which indicate the transition between metal species being plated by the bath. The open circuit potential of the bath is monitored by a potentiostat and compared with a setpoint open circuit potential which represents a desired metal species on the pourbaix diagram. The monitored open circuit potential and the setpoint are utilized to derive an error voltage. The error voltage will control the concentration of a chemical constitutent of the plating bath to maintain the desired method species on the plating surface.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: September 8, 1987
    Assignee: International Business Machines Corporation
    Inventors: Donald G. McBride, Robert G. Rickert
  • Patent number: 4692344
    Abstract: A method for forming a dielectric film over a semiconductor device is disclosed. The body of semiconductor material is formed and a hydrogen-containing silicon nitride material substantially free of silicon-hydrogen bonds is formed thereover.Also disclosed is a semiconductor device, including a body of semiconductor material and a dielectric film thereover. The dielectric film is a hydrogen-containing silicon nitride material substantially free of silicon-to-hydrogen bonds.
    Type: Grant
    Filed: February 28, 1986
    Date of Patent: September 8, 1987
    Assignee: RCA Corporation
    Inventors: Grzegorz Kaganowicz, Alfred C. Ipri, Richard S. Crandall
  • Patent number: 4692349
    Abstract: Selective electroless plating of cobalt or nickel is utilized to form conductive plugs in high-aspect-ratio vias in VLSI devices. Particularly good results are obtained when an active or catalytic film is formed on the via bottoms to serve as a plating base.
    Type: Grant
    Filed: March 3, 1986
    Date of Patent: September 8, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: George E. Georgiou, Gary N. Poli
  • Patent number: 4692348
    Abstract: A technique is described for producing very shallow doped regions in a substrate, at low temperatures. The doped regions are not in excess of about 300 angstroms in depth, and are formed at temperatures less than 700.degree. C. These shallow doped regions can be used in different applications, including the fabrication of semiconductor switching devices, diodes, and contacts. Overlayers containing the desired dopants are deposited on the substrate, after which an annealing step is carried out to institute the formation of a metallic compound. When the compound is formed, materials in the overlayers to be used as substrate dopants will be pushed ahead of the interface of the growing compound, and will be snowplowed into the top surface of the substrate, to produce the shallow doped region therein.
    Type: Grant
    Filed: July 28, 1986
    Date of Patent: September 8, 1987
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Rubloff, Marc F. Wittmer
  • Patent number: 4692786
    Abstract: Improved silicon semi-conductor device and process includes three layer sandwich passivation coating. The sandwich coating comprises first, a thin silica layer, preferably produced by oxidizing a silicon surface to the minimum thickness necessary to prevent interdiffusion of an overlying nitride layer with the silicon subsurface. The second layer of the sandwich construction is nitride and the third layer is a thicker layer of silica, preferably produced by plasma glass deposition which, together with the inner silica layer provides preselected electrical characteristics required of the composite barrier or passivation coating. This invention reduces manufacturing defects produced in conventional two layer passivation coatings, including a thicker silica inner layer, due to undercutting of the thicker silica inner layer upon etching to form terminal areas. Such undercutting is avoided by the thin silica inner layer in the present invention.
    Type: Grant
    Filed: August 21, 1986
    Date of Patent: September 8, 1987
    Inventor: Timothy M. Lindenfelser
  • Patent number: 4689246
    Abstract: A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.
    Type: Grant
    Filed: March 12, 1986
    Date of Patent: August 25, 1987
    Assignee: Itek Corporation
    Inventor: John R. Barrett
  • Patent number: 4687825
    Abstract: A method of manufacturing a phosphor screen of a cathode ray tube, comprises forming a pattern having a particle-receptive adhesive surface on an inner surface of a faceplate having a peripheral wall, rotating the faceplate about an axis perpendicular to its inner surface and passing its center, and charging phosphor particles onto the inner surface of the faceplate during or before rotation thereof so as to allow the phosphor particles to slide on the inner surface of the faceplate and to attach to the particle-receptive adhesive surface. The method can form a phosphor film having a uniform and sufficient thickness without an irregularity in the amount of phosphor attached.
    Type: Grant
    Filed: September 16, 1985
    Date of Patent: August 18, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Sagou, Takeo Itou
  • Patent number: 4687682
    Abstract: Sealing the backside of a semiconductor wafer prevents evaporation of the dopant (typically boron) when an epitaxial layer is grown on the front (active) side, thereby preventing autodoping of the epitaxial layer with excess dopant. The present technique deposits an oxide layer during the ramp-up of the furnace that also deposits the nitride cap, thereby avoiding an extra process step. It also avoids the higher temperatures required for the prior-art technique of growing the oxide layer, resulting in lower oxygen precipitation due to the capping process and a greater yield of usable wafers.
    Type: Grant
    Filed: May 2, 1986
    Date of Patent: August 18, 1987
    Assignee: American Telephone and Telegraph Company, AT&T Technologies, Inc.
    Inventor: Jeffrey T. Koze
  • Patent number: 4686559
    Abstract: An improved topside sealing of integrated circuit devices is disclosed which provided for hermetically sealing the top surface of the device comprising depositing a sealing layer of a nitride compound directly on the surface to be sealed. In a preferred embodiment, a protective layer may then be deposited over the nitride layer without any intervening masking steps being necessary.
    Type: Grant
    Filed: August 3, 1984
    Date of Patent: August 11, 1987
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Jacob D. Haskell
  • Patent number: 4686114
    Abstract: A method for deposition of metals onto a workpiece by applying a sensitizing solution to a workpiece, directing a high intensity optical beam onto the sensitized workpiece surface to flash evaporate sensitizer from the workpiece in areas which are not to be plated, and thereafter contacting the workpiece with an electroless plating solution to deposit a layer of metal in those areas from which the sensitizer is not flashed off.
    Type: Grant
    Filed: January 17, 1986
    Date of Patent: August 11, 1987
    Inventors: Michael J. Halliwell, Joseph Zahavi
  • Patent number: 4684544
    Abstract: Solder flux is applied to the face of a printed circuit board (24) or the like by flowing a foam (30) of liquid flux bubbles upwardly through the top of a chimney flue (10) and into contact with the board face which is top passed over the top of the flue. The size of bubbles adjacent the face of the board is controlled by placing a grid screen (26) within and immediately beneath the top of the flue. The openings (26a) in the grid screen allow passage therethrough of smaller bubbles (34) but prevent passage of larger bubbles (32). The force of the board face on the foam urges the larger bubbles downwardly into contact with the grid screen where the grid wires of the screen pierce and thereby break the larger bubbles into smaller bubbles which then rise to the face of the board.
    Type: Grant
    Filed: February 19, 1986
    Date of Patent: August 4, 1987
    Assignee: General Motors Corporation
    Inventor: Richard K. Arnett
  • Patent number: 4684542
    Abstract: A process for preparing tungsten silicide films using low pressure, low temperature chemical vapor deposition to deposit silicon-rich tungsten silicide films. As a source of silicon, higher order silanes, such as disilane and trisilane, are used. The gaseous tungsten source is WF.sub.6. The substrate temperature range is less than about 370.degree. C., while the total pressure range is in the range 0.05-1 Torr. WF.sub.6 flow rates are generally less than 25 sccm, while the higher order silane flow rates are generally less than about 400 sccm.
    Type: Grant
    Filed: August 11, 1986
    Date of Patent: August 4, 1987
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Jasinski, Bernard S. Meyerson, Bruce A. Scott
  • Patent number: 4684550
    Abstract: Electroless copper is plated from aqueous plating baths comprising a soluble copper salt, ethylenediamine tetraacetic acid, dimethylamine borane, thiodyglycolic acid and a surfactant reaction product of ethylene oxide and an acetylenic glycol.
    Type: Grant
    Filed: April 25, 1986
    Date of Patent: August 4, 1987
    Assignee: Mine Safety Appliances Company
    Inventors: John W. Milius, Jill D. Alderson
  • Patent number: 4683838
    Abstract: An insulator film can be formed at a low temperature without any damage to a substrate to be treated by a plasma in a plasma treatment system which comprises a magnetron for generating a microwave, an isolator for isolating a wave guide from the magnetron, a discharge tube for generating a plasma, the wave guide for leading the microwave from the magnetron to the discharge tube, a vacuum chamber integrally formed together with the discharge tube, an evaporation source provided in the vacuum chamber, a substrate to be treated and provided at a position to sandwich a stream of the plasma between the substrate and the evaporation source, electromagnets provided around the discharge tube and the vacuum chamber, and a manipulator for manipulating the substrate, the electromagnets generating a magnetic field to confine the stream of the plasma.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: August 4, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shin-Ichiro Kimura, Eiichi Murakami, Terunori Warabisako, Kiyoshi Miyake, Hideo Sunami
  • Patent number: 4684545
    Abstract: Nodule formation in a continuous electroless copper plating system is minimized by independently controlling the dissolved oxygen contents on the plating solution in the bath and in the associated external piping. The level of dissolved oxygen in the plating tank is maintained at a value such that satisfactory plating takes place. At the point where the plating solution leaves the tank, additional oxygen gas is introduced into the solution so that the level of dissolved oxygen in the plating solution in the external piping is high enough to prevent any plating from taking place in the external piping and so that in the external piping the copper is etched or dissolved back into solution. At the end of the external piping, the dissolved oxygen level is reduced so that the dissolved oxygen level of the plating solution in the tank is maintained at the level where plating will take place.
    Type: Grant
    Filed: February 10, 1986
    Date of Patent: August 4, 1987
    Assignee: International Business Machines Corporation
    Inventors: Edmond O. Fey, Peter Haselbauer, Dae Y. Jung, Ronald A. Kaschak, Hans-Dieter Kilthau, Roy H. Magnuson, Robert J. Wagner