Patents Examined by John D. Smith
  • Patent number: 4681778
    Abstract: A method and apparatus for making electrical connections between conductors on a substrate utilizes a dielectric-like metal film deposited on the substrate interconnecting the conductors to be connected. The dielectric-like film is deposited in the form of microscopic islands or columns that are spaced by microscopic distances, thus making the film non-conductive when deposited. When an electrical connection is desired, the dielectric-like film is melted by localized heating, for example, by a focused laser, thereby melting the individual metal islands and permitting them to flow together to make the film conductive.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: July 21, 1987
    Assignee: Optical Materials, Inc.
    Inventor: Peter L. Young
  • Patent number: 4681774
    Abstract: A method for maskless deposition of metals onto a workpiece by applying a sensitizing solution to a workpiece, directing a laser beam onto the sensitized workpiece surface to flash evaporate sensitizer from the workpiece in areas which are not to be plated, moving the workpiece or beam to describe a pattern, and thereafter contacting the thus-patterned sensitized workpiece with an electroless plating solution to deposit a layer of metal in those areas from which the sensitizer is not flashed off.
    Type: Grant
    Filed: January 17, 1986
    Date of Patent: July 21, 1987
    Inventors: Michael J. Halliwell, Joseph Zahavi
  • Patent number: 4681775
    Abstract: Cathode ray tubes with optical windows in the sidewall or funnel portion thereof are provided with transparent conductive films of metal oxide on the inner surface of the funnel in the window area. Such films provide electrical continuity with the internal conductive coating of the tube, while permitting optical viewing. The films are produced by in-situ pyrolysis of films of metal resiantes in organic solvents.
    Type: Grant
    Filed: March 13, 1985
    Date of Patent: July 21, 1987
    Assignee: North American Philips Consumer Electronics Corp.
    Inventor: Anthony V. Gallaro
  • Patent number: 4680246
    Abstract: A method for holding a hollow cylindrical body without a bottom without contacting the outside surface thereof and immersing the body in a liquid with which the outside surface of the cylindrical body is to be coated and preventing the liquid from contacting the inside wall of the cylindrical body. The method utilizes a device which includes device an inflatable elastic membrane which tightly contacts the inside wall of the cylindrical body so as to hold the body when it is inflated by supply of compressed fluid. The process for producing an electrophotographic element includes the steps of holding the hollow cylindrical body without a bottom, immersing the cylindrical body in a liquid containing a photosensitive material and separating the cylindrical body from the liquid to form a uniform photosensitive layer only on the outside surface thereof.
    Type: Grant
    Filed: June 6, 1986
    Date of Patent: July 14, 1987
    Assignee: Mitsubishi Chemical Industries Limited
    Inventors: Motohisa Aoki, Hironobu Iwanaga
  • Patent number: 4677937
    Abstract: A carrier for dual-in-line packages to be wave soldered, comprises a frame with tracks into which the packages can be slid. The tracks are defined by aligned upper and lower "U"-shaped channel members providing rails. Each track is defined between adjacent pairs of upper and lower members. Gates at either end of the tracks control movement of the packages into or out of the carrier. The carrier can be loaded and unloaded by means of apparatus including an inclined ramp on which the carrier can be releasably located, the packages being fed into the top of the ramp to fill the carrier, and sliding to the bottom of the ramp to empty the carrier of soldered packages prior to re-filling. Movement of the packages down the ramp is controlled by gates.
    Type: Grant
    Filed: July 30, 1985
    Date of Patent: July 7, 1987
    Assignee: Sun Industrial Coatings Private Ltd.
    Inventor: Sim Ah Tee
  • Patent number: 4676996
    Abstract: A method of producing a multiple thermocouple having a conductive open-cellular foam matrix, a portion of which forms a first pole with a plurality of discrete conductors of a different material from the foam matrix embedded in the foam having a portion of each of the discrete conductors being exposed on the insides of the cells of the foam forming a plurality of thermocouples. The remaining surface area inside the foam's cells not having an exposed discrete conductor thereon can be insulated. A second pole member is provided. Means to contact the discrete conductors in the foam and convey current produced by the thermocouples to the second pole of the thermocouple completes the multiple thermocouple. Such means to contact the discrete conductors can provide the heat to excite the thermocouples or such heat can come from other sources.
    Type: Grant
    Filed: August 27, 1986
    Date of Patent: June 30, 1987
    Inventor: Gregory R. Brotz
  • Patent number: 4674442
    Abstract: High purity oxidation is produced on a semiconductor substrate. The process includes heating the semiconductor substrate in the presence of an oxidizing ambient in a multi-walled reaction chamber containing a heating element. A halogen-containing ambient flows in an outer portion of the reaction chamber intermediate between the inner portion and the heating element to react with heating element contaminant. In a portion of the reaction chamber position intermediate of the inner portion and the outer portion, a gaseous ambient flows to remove water by-product from the reaction with the halogen which occurs in the outer portion of the reaction chamber. The apparatus for carrying out the above process is also provided.
    Type: Grant
    Filed: May 20, 1986
    Date of Patent: June 23, 1987
    Assignee: International Business Machines Corporation
    Inventor: Samuel E. Blum
  • Patent number: 4675207
    Abstract: The invention relates to a process for the depositing on a substrate a thin film or layer of a compound having at least one cationic constituent C and at least one anionic constituent A, such as zinc sulphide.On the substrate are formed at least two superimposed ionic layers respectively incorporating the said cationic constituent or constituents C and the said anionic constituent or constituents A by successively immersing the substrate in a first solution e.g. containing a salt of C, such as zinc sulphate and in a second solution eg containing a salt of A, such as sodium sulphide, while rinsing the substrate between two immersion operations.
    Type: Grant
    Filed: August 13, 1985
    Date of Patent: June 23, 1987
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Yann F. Nicolau
  • Patent number: 4673592
    Abstract: The present invention discloses a method for planarizing contact holes, vias, and other surface depressions, during the fabrication of an integrated circuit structure. Differential thermal conductivities are exploited to selectively remove a deposited film of metal from high-thermal-resistance areas, such as silicon dioxide or other insulators, and not from low-thermal-resistance areas, such as silicon or metal. By repetition of this step, very deep depressions, having a high aspect ratio, are reliably filled.
    Type: Grant
    Filed: June 2, 1982
    Date of Patent: June 16, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Vernon R. Porter, Samuel C. Baber
  • Patent number: 4673593
    Abstract: A semiconductor device having an ohmic electrode which has formed on the surface of a p-type III-V compound semiconductor an assembly of a first Ti layer, a second Zn layer, a third metal layer made of one element selected from among Pt, Mo, W and Cr, and a fourth Au layer is disclosed. A process for producing such semiconductor device is also disclosed.The present invention provides a novel ohmic electrode having a low contact resistance comparable to that of a conventional electrode formed by deposition of successive Au, Zn and Au layers. The novel electrode also has the advantage of another conventional electrode wherein the Au electromigration is held to a minimum by forming an assembly of a Ti layer, a metal layer made of an element selected from among Pt, Mo, W and Cr, and an Au layer.
    Type: Grant
    Filed: March 4, 1985
    Date of Patent: June 16, 1987
    Assignee: Sumitomo Electric Industries Ltd.
    Inventor: Takeshi Himoto
  • Patent number: 4671968
    Abstract: A method of electrolessly depositing copper onto a suitably prepared substrate surface is disclosed in which passivity to an otherwise autocatalytic electroless depositing solution is cured by application of a cathodic current for a brief period of time until autocatalytic deposition commences. The method is suitable for coating surfaces which per se are passive to the depositing solution as well as for coating surfaces which normally are receptive to the autocatalytic deposition and which have been so coated up to a certain point where interruption of the plating thereafter renders the surface passive to further deposition.
    Type: Grant
    Filed: August 6, 1986
    Date of Patent: June 9, 1987
    Assignee: MacDermid, Incorporated
    Inventor: Leo J. Slominski
  • Patent number: 4672023
    Abstract: A method for filling indentations to planarize the surface of a wafer is disclosed. The method includes three steps: (1) coating the wafer surface with a layer of positive photoresist that fills the indentations and covers the surface of the wafer; (2) exposing the layer of photoresist to light or other radiation source of such intensity and duration that the layer of photoresist is exposed down to the surface of the wafer but not into the indentations; and (3) removing the exposed portion of the photoresist by using a developer, resulting in a planarized wafer containing indentations filled with unexposed photoresist. Once the wafer has been planarized by this method, overstructures can be formed over the top of the photoresist filled indentations.
    Type: Grant
    Filed: October 21, 1985
    Date of Patent: June 9, 1987
    Assignee: Avantek, Inc.
    Inventor: Charles C. Leung
  • Patent number: 4671970
    Abstract: A process for forming planar trench oxide isolated integrated circuit devices. In particular, the process fills trenches of diverse widths, yet provides a final structure in which the narrow trench dielectrics, the wide trench dielectrics, and the active region surfaces are substantially coplanar. Furthermore, the process reduces the likelihood of creating voids in the narrow trenches. According to one practice, following the formation of the trenches in the substrate, successive layers of conformal silicon nitride, conformal polysilicon, and relatively conformal CVD oxide are formed to the relative depth of the trenches. A photoresist mask is then first selectively formed over the central regions of the wide trenches and then used as a mask during the anisotropic etch of exposed oxide. The underlying polysilicon layer serves as an oxide etchant stop, and also provides the material from which the next successive oxidation partially fills the previously etched regions with thermal silicon dioxide.
    Type: Grant
    Filed: February 5, 1986
    Date of Patent: June 9, 1987
    Assignee: NCR Corporation
    Inventors: Alan E. Keiser, Randall S. Mundt
  • Patent number: 4670306
    Abstract: A method for the treatment of a substrate for electroless metal plating which includes the steps of applying onto at least a portion of the substrate a material selected for having adequate adherence to the substrate and for being suitably absorptive of an electroless plating cataylst. The coated surface is thereafter successively contacted with a plating catalyst, accelerator for the catalyst, and an electroless plating solution.
    Type: Grant
    Filed: September 9, 1985
    Date of Patent: June 2, 1987
    Assignee: Seleco, Inc.
    Inventor: Robert A. Salem
  • Patent number: 4670297
    Abstract: A first masking layer of a first resist is provided over a semiconductor substrate and is patterned in a selected region to provide a masked region over which an airbridge interconnect will be provided. A second relatively thick layer of a second, different type of resist and a third relatively thin layer of resist are provided, respectively, over the substrate. The second and third layers of resist are patterned to provide an aperture having overhanging portions exposing the previously applied patterned regions of the first layer, and selected adjacent portions of the substrate. The second and third layers may also be patterned to provide a region for a patterned strip conductor. A stream of evaporated metal is directed towards the substrate and deposited within the apertures to provide an airbridge interconnect conductor and patterned strip conductor.
    Type: Grant
    Filed: June 21, 1985
    Date of Patent: June 2, 1987
    Assignee: Raytheon Company
    Inventors: Kyu-Woong Lee, Mark S. Durschlag, John Day
  • Patent number: 4670298
    Abstract: A fluorescent solder paste mixture comprising a fluorescent pigment dispersed in a solder paste is disclosed. The solder paste comprises solder fragments dispersed in a solder flux. A method for making the solder paste mixture and a method for using the solder paste mixture to make a fluorescent solder joint between an electrical component and a circuit board are also disclosed. Use of the fluorescent solder paste mixture facilitates automatic and manual inspection of circuit boards during and after assembly.
    Type: Grant
    Filed: December 9, 1985
    Date of Patent: June 2, 1987
    Assignee: Northern Telecom Limited
    Inventors: James A. Lucas, William P. Trumble
  • Patent number: 4670325
    Abstract: A structure comprising on a substrate successive layers of metal circuitry having therebetween as a dielectric a cured polyimide composition containing a polyimide and aluminum oxide or zinc oxide or mixtures thereof.The structure is produced by a method including the following process steps:blanket screen printing a mixture containing a polyamido carboxylic acid, aluminum oxide or zinc oxide or mixtures thereof and a detackifier with the rest being a solvent on a substrate with a layer of metal circuitry thereon,drying the deposited layer at a temperature between about 25.degree. and about 120.degree. C.,selectively etching holes into the deposited layer where vias between adjacent layers of metal circuitry are needed,curing the deposited layer at a temperature between about 300.degree. and about 400.degree. C. andforming another layer of metal circuitry.
    Type: Grant
    Filed: July 2, 1986
    Date of Patent: June 2, 1987
    Assignee: IBM Corporation
    Inventors: Peter Bakos, Russell E. Darrow, Nelson P. Franchak, Joseph Funari
  • Patent number: 4669178
    Abstract: A method of forming a low resistance path, e.g., to serve as a guard ring, in a silicon semiconductor device is disclosed.An opening is defined in an upper protective layer and an underlying lower protective layer. Normally these layers are silicon nitride and silicon dioxide, respectively. The lower protective layer is isotropically wet etched so that the upper protective layer overhangs the lower protective layer and protects a part of the silicon wafer surface.A first impurity is implanted in the exposed silicon wafer surface except in the annular area protected by the upper protective layer overhang.A silicon dioxide layer is grown on the entire exposed surface of the silicon wafer which is inherently thicker over the area where the impurity has been implanted and inherently thinner over the annular area where the impurity has not been implanted. The upper protective layer is then preferably removed.
    Type: Grant
    Filed: May 23, 1986
    Date of Patent: June 2, 1987
    Assignee: International Business Machines Corporation
    Inventor: Eric D. Johnson
  • Patent number: 4668533
    Abstract: Imagewise deposition of ink onto a substrate such as a circuit board, by ink jet technology, to produce a metal-imaged circuit board.
    Type: Grant
    Filed: May 10, 1985
    Date of Patent: May 26, 1987
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Joel S. Miller
  • Patent number: 4666786
    Abstract: A composite nickel plated sliding surface is obtained by the formation of a composite nickel plating film on a sliding surface of an automobile part such as an engine cylinder or piston by electroless nickel plating. The plating film contains at least one member of wear resistant particles having an average particle size of 0.1 to 1.0.mu. selected from SiC, TiC, WC, BC.sub.4, TiN, Al.sub.2 O.sub.3 or the like, and also at least one member of lubricating particles having an average particle size of 1 to 10.mu. selected from BN, MoS.sub.2, and Teflon. The nickel plating bath is adjusted to have a phosphorus concentration of 0.5 to 12%. When the matrix of the nickel plating film has a phosphorus concentration of 0.5 to 5%, the film hardness is improved.
    Type: Grant
    Filed: February 27, 1985
    Date of Patent: May 19, 1987
    Assignees: Aisin Seiki Kabushiki Kaisha, Toyota Jidosha Kabushiki Kaisha
    Inventors: Hideo Yano, Keiichi Kano, Hitoshi Ozawa, Shinji Kato, Yoshio Takagi