Patents Examined by John F. Niebling
  • Patent number: 7230877
    Abstract: A method for fabricating a semiconductor memory device is described. An insulating layer is disposed on a semiconductor substrate. A matrix of semiconductor memory elements is disposed in the substrate. The semiconductor memory elements include a plurality of contact holes formed in the insulating layer. One contact hole is formed in the insulating layer for each of the semiconductor memory elements. A bit definition region is disposed in the semiconductor substrate underneath each of the contact holes. A contact plug is disposed in each of the contact holes and is in electrical contact with the bit definition region. The bit definition region is configured such that a contact resistance between the semiconductor substrate and the contact plug defines a bit to be stored in the semiconductor memory elements, An evaluation circuit is connected to and evaluates the contact resistance of the semiconductor memory elements.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: June 12, 2007
    Assignee: Infineon Technologies AG
    Inventors: Andreas Rusch, Steffen Rothenhäusser, Alexander Truby, Yoichi Otani, Ulrich Zimmermann
  • Patent number: 7198962
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: April 3, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 7154605
    Abstract: A method is described for characterizing defects on a test surface of a semiconductor wafer using a confocal-microscope-based automatic defect characterization (ADC) system. The surface to be tested and a reference surface are scanned using a confocal microscope to obtain three-dimensional images of the test and reference surfaces. The test and reference images are converted into sets of geometric constructs, or “primitives,” that are used to approximate features of the images. Next, the sets of test and reference primitives are compared to determine whether the set of test primitives is different from the set of reference primitives. If such a difference exists, then the difference data is used to generate defect parameters, which are then compared to a knowledge base of defect reference data. Based on this comparison, the ADC system characterizes the defect and estimates a degree of confidence in the characterization.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: December 26, 2006
    Assignee: KLA-Tencor Corporation
    Inventors: Bruce W. Worster, Ken K. Lee
  • Patent number: 7109788
    Abstract: An apparatus and method of improving impedance matching between a RF signal and a multi-segmented electrode in a plasma reactor powered by the RF signal. The apparatus and method phase shifts the RF signal driving one or more electrode segment of the multi-segmented electrode, amplifies the RF signal, and matches an impedance of the RF signal with an impedance of the electrode segment, where the RF signal is modulated prior to matching of the impedance of the RF signal. The apparatus and method directionally couples an output of the matching of the impedance of the RF signal and the electrode segment, and adjusts the output of the matching of the impedance of the RF signal such that a directionally coupled output signal and a reference signal representing the RF signal at the output of the master RF oscillator produces a demodulated signal of minimal amplitude.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: September 19, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Jovan Jevtic, Andrej Mitrovic
  • Patent number: 7101721
    Abstract: An adaptive manufacturing process for a Film Bulk Acoustic Resonator (FBAR) tests the FBAR circuit during manufacturing to determine a resonant frequency thereof. Reactive tuning elements may be adjusted as needed depending on the testing to change the resonant frequency to a desired resonant frequency. In an exemplary embodiment, predetermined masks may be applied to modify the tuning elements.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 5, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Jon D. Jorgenson, David Dening, Victor Steel
  • Patent number: 7079433
    Abstract: A wafer level burn-in method for static-random access memory. The SRAM memory has a plurality of word lines and a plurality of bit lines. The SRAM memory also has pull up circuits and equalizer circuits connected to various bit lines. All the word lines are switched on for testing any leakage in the gate dielectric layer. A high potential is applied to a bit line of every bit line pairs and a low potential is applied to the other bit line of the bit line pairs. The pull-up circuits and the equalizer circuits are shut down. The current at a steady state is used to judge the normality of an SRAM chip.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: July 18, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hung Chen, Te-Sun Wu
  • Patent number: 7049586
    Abstract: Bright and dark field imaging operations in an optical inspection system occur along substantially the same optical path using the same light source by producing either a circular or an annular laser beam. Multiple beam splitting is achieved through the use of a diffractive optical element having uniform diffraction efficiency. A confocal arrangement for bright field and dark field imaging can be applied with multiple beam scanning for suppressing the signal from under-layers. A scan direction not perpendicular to the direction of movement of a target provides for improved die-to-die comparisons.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: May 23, 2006
    Assignee: Applied Material Israel, Ltd.
    Inventor: Silviu Reinhorn
  • Patent number: 7045430
    Abstract: A dielectric film containing LaAlO3 and method of fabricating a dielectric film contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO3 gate dielectric is formed by atomic layer deposition employing a lanthanum sequence and an aluminum sequence. A lanthanum sequence uses La(thd)3 (thd=2,2,6,6-tetramethyl-3,5-heptanedione) and ozone. An aluminum sequence uses either trimethylaluminum, Al(CH3)3, or DMEAA, an adduct of alane (AlH3) and dimethylethylamine [N(CH3)2(C2H5)], with distilled water vapor.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: May 16, 2006
    Assignee: Micron Technology Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7038481
    Abstract: A method and apparatus for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. A memory device associated with the method of the present invention is also disclosed.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Kenneth W. Marr
  • Patent number: 7026187
    Abstract: A method of employing organic vapor phase deposition to fabricate a polycrystalline organic thin film is described. By employing organic vapor phase deposition at moderate deposition chamber pressures and substrate temperatures, a polycrystalline organic thin film results having significantly larger purity and grain size than what is achievable by vacuum thermal evaporation. These polycrystalline organic thin films may be employed in a variety of applications, including, for example, organic light emitting devices, photovoltaic cells, photodetectors, lasers, and thin film transistors.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: April 11, 2006
    Assignee: The Trustees of Princeton University
    Inventors: Max Shtein, Stephen R. Forrest
  • Patent number: 7018873
    Abstract: provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: March 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Wilfried E. Haensch, Hussein I. Hanafi
  • Patent number: 7018860
    Abstract: A method of preventing the cathode of an active matrix organic light emitting diode from breaking. A substrate having an array of thin film transistors thereon is provided. Each thin film transistor includes a gate electrode, a channel layer, a source terminal and a drain terminal. A passivation layer is formed over the substrate and then the passivation layer is planarized. Thereafter, an opening that exposes the drain terminal is formed in the passivation layer. An anode layer is formed over the passivation layer and the interior of a portion of the opening so that the drain terminal and the anode layer are electrically connected. A light-emitting layer and a cathode layer are sequentially formed over the substrate to form an active matrix organic light emitting device.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: March 28, 2006
    Assignee: Au Optronics Corporation
    Inventors: Hsin-Hung Lee, Chih-Hung Su, Yi Sheng Cheng
  • Patent number: 7015057
    Abstract: A data holding control signal for each data line is supplied to a plurality of source followers that are connected together in parallel. The parallel-connected source followers are a combination of at least one first follower that is illuminated with laser light only once and at least one second follower that is illuminated twice. A width of the laser light illumination for crystallization is equal to a pitch of the source followers multiplied by an integer that is not less than 3.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: March 21, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Yuji Kawasaki
  • Patent number: 7015107
    Abstract: When a dummy sidewall and source and drain regions are once formed and then the dummy sidewall is removed to extend the source and drain regions, the removal of the dummy sidewall is performed after formation of a protective oxide film on a gate electrode and on the major surfaces of the source and drain regions. This efficiently prevents conventional surface roughness of the upper surface of the gate electrode and the impurity region due to the removal of the dummy sidewall.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: March 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kohei Sugihara, Hirokazu Sayama
  • Patent number: 6989073
    Abstract: A semiconductor device manufacturing system has a vacuum chamber which is provided with a cathode electrode for holding a substrate to be processed and into which a reactive gas for generating discharging plasma by the application of a high-frequency electric power is introduced, a measuring circuit which measures at least one of the impedance of a system including the plasma, the peak-to-peak voltage of a high-frequency signal applied to the plasma, and a self-bias voltage applied to the cathode electrode, and a sense circuit which compares the measured value from the measuring circuit with previously prepared data and senses the change of processing characteristics with time for the substrate in using the discharging plasma or the cleaning time of the inside of the vacuum chamber.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takanori Matsumoto, Satoshi Shimonishi, Fumio Sato, Masaki Narita
  • Patent number: 6985291
    Abstract: A film that includes a first reflective polarizer substantially reflecting light having a first polarization state and substantially transmitting light having a second polarization state, a polarization rotating layer or depolarizing layer (or both) positioned to receive light passing through the first reflective polarizer, and a second reflective polarizer positioned to receive light passing through the polarization rotating layer or depolarizing layer, the second reflective polarizer substantially reflecting light having a third polarization state back through the polarization rotating layer or depolarizing and substantially transmitting light having a fourth polarization state. Articles containing the film can be formed.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: January 10, 2006
    Assignee: 3M Innovative Properties Company
    Inventors: Philip E. Watson, Keith M. Kotchick, Richard C. Allen
  • Patent number: 6984198
    Abstract: Systems, methods and mediums are provided for automating experiments within an automated environment without the need to disassociate the test subject (e.g., the semiconductor chip or chips) from that environment. An “experiment” may be a pre-planned deviation of an established (e.g., pre-defined) process utilizing the automated environment. A computer-implemented method, system and computer-readable medium for managing experiments, such as those relating to semiconductor technology. An experiment order includes some deviation from a base process capable of operating in an automated environment. An approval of the experiment order is obtained from a distribution list of users, while permitting the users to attach documents to the experiment order or perhaps modify the experiment. The experiment order is translated into processing data suitable for implementation by said automated environment, and stored.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: January 10, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Badri N. Krishnamurthy, Parris C. M. Hawkins
  • Patent number: 6979578
    Abstract: A method of determining a parameter of interest during processing of a patterned substrate includes obtaining a measured net reflectance spectrum resulting from illuminating at least a portion of the patterned substrate with a light beam having a broadband spectrum, calculating a modeled net reflectance spectrum as a weighted incoherent sum of reflectances from different regions constituting the portion of the patterned substrate, and determining a set of parameters that provides a close match between the measured net reflectance spectrum and the modeled net reflectance spectrum. For wavelengths below a selected transition wavelength, a first optical model is used to calculate the reflectance from each region as a weighted coherent sum of reflected fields from thin film stacks corresponding to laterally distinct areas constituting the region. For wavelengths above the transition wavelength, a second optical model based on effective medium approximation is used to calculate the reflectance from each region.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 27, 2005
    Assignee: Lam Research Corporation
    Inventor: Vijayakumar C. Venugopal
  • Patent number: 6964892
    Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Rama Divakaruni, Louis Lu-Chen Hsu, Yujun Li
  • Patent number: 6955870
    Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: October 18, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki