Patents Examined by John F. Niebling
  • Patent number: 6884672
    Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: April 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Karanam Balasubramanyam, Serge Biesemans, Byeongju Park
  • Patent number: 6884638
    Abstract: A method for fabricating a flash memory device by determining the active region width (10) of a semiconductor device (27) using a measuring technique for the source drain overdrive current elements (31, 32, 33) having different active region widths and using that difference to establish the difference between the active region width of the devices (31, 32, 33) and the drawn width and using the difference to establish the actual width (10) from drawn width in future devices, and a device thereby fabricated.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: April 26, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tien-Chun Yang, Nian Yang, Zhigang Wang
  • Patent number: 6884734
    Abstract: A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the blocking layer and the substrate to form the line segment with a second dimension across the line segment that is smaller than the first dimension. The blocking layer prevents the formation of reaction product on the hard mask so that the initial thickness of the hard mask is maintained. The blocking layer can also serve as an ARC layer for photoresist patterning so that the use of an additional film layer is not required.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: April 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Frederick W. Buehrer, Derek Chen, William Chu, Scott Crowder, Sadanand V. Deshpande, David V. Horak, Wesley C. Natzle, Hung Y. Ng, Len Y. Tsou, Chienfan Yu
  • Patent number: 6884705
    Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: April 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa Sung Rhee, Nae In Lee, Jung Il Lee, Sang Su Kim, Bae Geum Jong
  • Patent number: 6881595
    Abstract: Electronic circuits or the parts thereof on printed circuit boards are tested by detecting infrared radiation emitted by the surface of the circuit. The detected radiation is converted to data that represent a surface structure and/or depth structure of the circuit. Deviation between the data representing the detected surface structure and/or depth structure and data representing the desired stated of the surface structure and/or depth structure are determined.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: April 19, 2005
    Inventor: Werner Reisinger
  • Patent number: 6881631
    Abstract: A method of manufacturing a semiconductor device comprises forming a first conductive material film on a semiconductor substrate with a gate insulating film interposed therebetween, selectively forming a second conductive material film on the first conductive material film, the second conductive material film being capable of reducing the first conductive material film, causing that portion of the first conductive material film which is selectively covered with the second conductive material film to be subjected to a reducing reaction with the second conductive material film so as to change the composition of the resultant film and to form a third conductive material film differing in the work function from the first conductive material film, and forming a first gate electrode having the first conductive material film and a second gate electrode having at least the third conductive material film and differing from the first gate electrode in the work function.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: April 19, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro Saito, Kyoichi Suguro
  • Patent number: 6881649
    Abstract: A plurality of micromirror chips are collectively made from a common substrate. Each of the micromirror chips is formed with a micromirror unit including a frame, a mirror-forming portion separate from the frame via spaces, and torsion bars connecting the mirror-forming portion to the frame. The common substrate is subjected to etching to provide the spaces and make division grooves for dividing the common substrate into the individual micromirror chips. The etching for the spaces and the etching for the division grooves are performed in parallel with each other.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: April 19, 2005
    Assignees: Fujitsu Limited, Fujitsu Media Devices Limited
    Inventors: Norinao Kouma, Yoshihiro Mizuno, Hisao Okuda, Ippei Sawaki, Osamu Tsuboi, Yoshitaka Nakamura
  • Patent number: 6881634
    Abstract: In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: April 19, 2005
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jeffrey T. Watt
  • Patent number: 6881650
    Abstract: A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Il Lee, Kazuyuki Fujihara, Nae-In Lee, Geum-Jong Bae, Hwa-Sung Rhee, Sang-su Kim
  • Patent number: 6882018
    Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: April 19, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Etsuko Fujimoto
  • Patent number: 6882745
    Abstract: Systems and methods are described for translating detected wafer defect coordinates to reticle coordinates using CAD data. A wafer inspection image is provided and coordinates of potential defects in the wafer are determined. Then the wafer inspection image is converted into a predetermined image format. CAD data for the device under test is then used to produce a second image, also in the predetermined image format. The CAD-derived image and the wafer-derived image are then aligned, and the coordinates of potential defects in the wafer are converted into CAD coordinates. The CAD coordinates are then used to navigate through the reticle for the wafer in order to locate reticle defects corresponding to the detected wafer defects.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 19, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Keith Brankner, David M. Schraub
  • Patent number: 6878641
    Abstract: Precursor compositions for the CVD formation of low k dielectric films on a substrate, e.g., as an interlayer dielectric for fabrication of microelectronic device structures. The precursor composition includes a gaseous mixture of (i) at least one aromatic compound, (ii) an inert carrier medium and (iii) optionally at least one unsaturated constituent that is ethylenically and/or acetylenically unsaturated The unsaturated constituent can include either (a) a compound containing ethylenic unsaturation and/or acetylenic unsaturation, or (b) an ethylenically unsaturated and/or acetylenically unsaturated moiety of the aromatic compound (i) of the precursor composition. The low k dielectric film material may be usefully employed in integrated circuitry utilizing copper metallization, to achieve low RC time constants and superior microelectronic device performance.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: April 12, 2005
    Assignee: Advanced Technology Materials, Inc.
    Inventor: Neil H. Hendricks
  • Patent number: 6878644
    Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; curing the layer of spin-on glass material by exposing the spin-on glass material to electron beam radiation at a first temperature for a first period and subsequently exposing the spin-on glass material to an electron beam at a second temperature for a second period, where the second temperature is greater than the first temperature. The method concludes by depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: April 12, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Rick J. Roberts, Michael S. Cox, Jun Zhao, Khaled Elsheref, Alexandros T. Demos
  • Patent number: 6878603
    Abstract: In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: April 12, 2005
    Assignee: Atmel Germany GmbH
    Inventors: Christoph Bromberger, Franz Dietz, Volker Dudek, Michael Graf, Joern Herrfurth, Manfred Klaussner
  • Patent number: 6878598
    Abstract: Provided is a method of forming a thick metal silicide layer on a gate electrode. The method includes forming a gate electrode of a transistor on a semiconductor substrate, wherein a hard mask is formed on the gate electrode, forming a spacer on a sidewall of the gate electrode, forming a first silicide layer on a portion of the semiconductor substrate, adjacent to the spacer, forming an insulating layer on the first suicide layer to expose upper portions of the hard mask and the spacer, selectively etching the exposed upper portions of the hard mask and the spacer using the insulating layer as an etch mask until the top surface and the sidewall of the gate electrode are exposed, forming a metal layer on the exposed top surface and sidewall of the gate electrode, and forming a second silicide layer on the gate electrode by siliciding the metal layer.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: April 12, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-won Jun, Kong-soo Cheong, Jeong-ho Shin
  • Patent number: 6878574
    Abstract: An alloying method includes steps of forming a metal layer on a semiconductor that is then transferred to a material having a low thermal conductivity. An interface between the semiconductor and the metal layer is formed into an alloy by irradiating the interface with a laser beam having a wavelength that is absorbable in at least one of the semiconductor and the metal layer. Preferably, the material having a low thermal conductivity is a resin or amorphous silicon. Because the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effects on the characteristics of the semiconductor device.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: April 12, 2005
    Assignee: Sony Corporation
    Inventors: Katsuhiro Tomoda, Toyoharu Ohata
  • Patent number: 6878583
    Abstract: A new process integration method is described to form heavily doped p+ source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p+ doping of the poly-silicon gate and S/D regions around the PMOS gate, B+ ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: April 12, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Jyh Chyurn Guo
  • Patent number: 6878577
    Abstract: A method of forming an LDD of a semiconductor device. A substrate having a polysilicon layer thereon is provided, wherein the polysilicon layer comprises a first region and a second region. A patterned photoresist layer is formed on the polysilicon layer for exposing the first region and covering the second region. The photoresist layer covering the second region comprises a middle portion and an edge portion, wherein the middle portion is thicker than the edge portion. Then, an ion implantation process is performed using the photoresist layer as a mask for forming a source/drain in the first region of the polysilicon layer and an LDD in the second region underneath the edge portion of the photoresist layer.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: April 12, 2005
    Assignee: Au Optronics Corporation
    Inventor: Ming-Sung Shih
  • Patent number: 6878559
    Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: April 12, 2005
    Assignees: Applied Materials, Inc., Advanced Micro Devices, Inc.
    Inventors: Peter G. Borden, G. Jonathan Kluth, Eric Paton
  • Patent number: 6878560
    Abstract: A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 12, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian