Patents Examined by John F. Niebling
  • Patent number: 6955930
    Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: October 18, 2005
    Assignee: Credence Systems Corporation
    Inventors: Erwan Le Roy, Chun-Cheng Tsao
  • Patent number: 6955264
    Abstract: In order to provide a method of detecting protrusion of an inspection object from a palette improved to be capable of making highly precise detection and reducing a socket breakage ratio, an inspection object is introduced into each of a plurality of pockets provided on the surface of a palette, which in turn is transported. A reflection level of the inspection object stored in each of the plurality of pockets is measured every palette with a reflection type photoelectric sensor. The maximum value and the minimum value of the reflection level are obtained from data of every palette, for calculating a dispersion width defined by the difference between the maximum value and the minimum value. The dispersion width is compared with a previously set determination threshold, for determining whether or not the dispersion width is greater than the determination threshold.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Ijichi, Shinji Semba
  • Patent number: 6953705
    Abstract: A method of dry etching a performance sensitive element of an organic electronic device, said method comprising the steps of: (a) having at least one performance sensitive element on the substrate spaced apart from a first conductive member, wherein at least one of the performance sensitive elements is a conductive lead; (b) placing organic material on the performance sensitive element and the first conductive member, (c) forming a patterned conductive layer over the organic material exposing a predetermined portion of the performance sensitive elements; and (d) dry etching the organic material in the exposed areas of the performance sensitive elements using at least one oxygen-containing gas, and organic electronic device created using said process.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: October 11, 2005
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: Shiva Prakash
  • Patent number: 6953979
    Abstract: A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: October 11, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
  • Patent number: 6952269
    Abstract: A method for adiabatically heating semiconductor device surfaces, including using capping layers to prevent deformation of surfaces. Using the method, semiconductor surfaces having varying topographies or topologies may be heated adiabatically. In an embodiment of the method, one or more capping layers may be formed over a semiconductor surface, to further prevent deformation of semiconductor surfaces.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: Jose A. Maiz, Sarangapani Sista, Mark Liu
  • Patent number: 6949452
    Abstract: There is provided a method for fabricating an image display device having an active matrix substrate including high-performance transistor circuits operating with high mobility as drive circuits for driving pixel portions which are arranged as a matrix. The portion of a polysilicon film formed in a drive circuit region DAR1 provided on the periphery of the pixel region PAR of the active matrix substrate SUB1 composing the image display device is irradiated and scanned with a pulse modulated laser beam or a pseudo CW laser beam to be reformed into a quasi-strip-like-crystal silicon film having a crystal boundary continuous in the scanning direction so that discrete reformed regions each composed of the quasi-strip-like-crystal silicon film are formed.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: September 27, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Mutsuko Hatano, Shinya Yamaguchi, Takeo Shiba, Mitsuharu Tai, Hajime Akimoto
  • Patent number: 6946343
    Abstract: A manufacturing method of an integrated chip. The integrated chip includes at least two devices with different functions. The method uses a first production line to form a first device on a semiconductor wafer and then uses a second production line to form a second device on the semiconductor wafer so as to complete the integrated chip.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: September 20, 2005
    Assignee: United Microelectronics Corp.
    Inventor: Fu-Tai Liou
  • Patent number: 6946303
    Abstract: The present invention is a system for creating a signature of a substrate manufactured in a semiconductor or data storage fabrication facility. A central processing unit is configured to receive external sensor data from a plurality of equipment-types located within the facility and integrate the external sensor data, by combining the data into a unitary whole, to create the signature for the substrate. Additionally, the present invention is a method for creating a signature of the substrate by selecting a substrate from the facility process line, receiving external sensor data associated with the substrate from a plurality of equipment-types, and integrating the external sensor data associated with the substrate to create the signature of the substrate. The created substrate signature may also be compared with other substrate signatures to electronically diagnose a process, equipment associated with the process, or a processed substrate.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: September 20, 2005
    Assignee: Lam Research Corporation
    Inventors: Janet M. Flanner, James C. Vetter
  • Patent number: 6943575
    Abstract: A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Circuits and system associated with the method of the present invention are also disclosed.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: September 13, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Kenneth W. Marr
  • Patent number: 6943055
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Patent number: 6944370
    Abstract: A method of processing a semiconductor wafer that has circuits in each of a plurality of regions sectioned by a plurality of streets on the front surface and has a coating layer formed on the front surface having the circuits to a predetermined thickness, the method comprising a stress-reducing step of reducing the stress of the coating layer by forming a plurality of grooves in the coating layer formed on the front surface of the semiconductor wafer; and a grinding step of processing the back surface of the semiconductor wafer by grinding to a predetermined thickness after the stress-reducing step.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: September 13, 2005
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 6943066
    Abstract: An electronic device is formed from electronic elements deposited on a substrate. The electronic elements are deposited on the substrate by advancing the substrate through a plurality of deposition vacuum vessels, with each deposition vacuum vessel having at least one material deposition source and a shadowmask positioned therein. The material from at least one material deposition source positioned in each deposition vacuum vessel is deposited on the substrate through the shadowmask positioned in the deposition vacuum vessel to form on the substrate a circuit comprised of an array of electronic elements. The circuit is formed solely by the successive deposition of materials on the substrate.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 13, 2005
    Assignee: Advantech Global, LTD
    Inventors: Thomas P. Brody, Paul R. Malmberg, David J. Stapleton, Robert E. Stapleton
  • Patent number: 6940112
    Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings
  • Patent number: 6939813
    Abstract: A plasma reactor comprises an electromagnetic energy source coupled to a radiator through first and second variable impedance networks. The plasma reactor includes a chamber having a dielectric window that is proximate to the radiator. A shield is positioned between the radiator and the dielectric window. The shield substantially covers a surface of the radiator near the dielectric window. A portion of the radiator that is not covered by the shield is proximate to a conductive wall of the chamber. Plasma reactor operation includes the following steps. A plasma is ignited in a chamber with substantially capacitive electric energy coupled from the radiator. A variable impedance network is tuned so that the capacitive electric energy coupled into the chamber is diminished. The plasma is then powered with substantially magnetic energy.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: September 6, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Kevin G. Donohoe
  • Patent number: 6936842
    Abstract: Embodiments of the invention provide an apparatus and method to determine the health of a substrate process such as, for example, a pre-clean process using plasma to remove copper oxide from a copper layer on a substrate, and the point at which the process has ended. In one aspect, optical characteristics and/or chamber impedance are used to determine the process end-point and/or process chamber health.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 30, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Suraj Rengarajan, Michael Wood, Haojiang Li, Moshe Sarfaty, Kevin Song
  • Patent number: 6936843
    Abstract: The present disclosure pertains to a method of preparing a test specimen for testing of the bonding strength of a layer of additive material to a crystalline substrate, or testing of the bonding strength of one layer of additive material to a second layer of additive material, where both layers of additive material overlie a crystalline substrate. The method includes both test specimen “cutting” from a large sample of material and preparation of an individual test specimen for four-point adhesion testing. Also described is a fixture which is useful for cutting the individual test specimen from the large sample of material.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 30, 2005
    Assignee: Applied Materials, Inc.
    Inventor: Zhenjiang Cui
  • Patent number: 6936547
    Abstract: The present invention is generally directed to a novel gas delivery system for various deposition processes, and various methods of using same. In one illustrative embodiment, a deposition tool comprises a process chamber, a wafer stage adapted for holding a wafer positioned therein, and a gas delivery system positioned in the chamber above a position where a plasma will be generated in the chamber, wherein substantially all of a reactant gas is delivered into the chamber via the gas delivery system. In another illustrative embodiment, the reactant gas exiting the gas delivery system is directed so as to cover substantially all of an area defined by an upper surface of the wafer.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: August 30, 2005
    Assignee: Micron Technology, Inc..
    Inventors: Weimin Li, Neal R. Rueger, Li Li, Ross S. Dando, Kevin T. Hamer, Allen P. Mardian
  • Patent number: 6934005
    Abstract: A first set of interferometric measuring beams is used to determine a location of a patterned surface of a reticle and a reticle focus plane for a reticle that is back clamped to a reticle stage. A second set of interferometric measuring beams is used to determine a map of locations of the reticle stage during scanning in a Y direction. The two sets of interferometric measuring beams are correlated to relate the reticle focal plane to the map of the reticle stage. The information is used to control the reticle stage during exposure of a pattern on the patterned surface of the reticle onto a wafer.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: August 23, 2005
    Assignee: ASML Holding N.V.
    Inventors: Stephen Roux, Todd J. Bednarek
  • Patent number: 6928635
    Abstract: One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: August 9, 2005
    Assignee: Numerical Technologies, Inc.
    Inventors: Dipankar Pramanik, Michael Sanie
  • Patent number: 6924178
    Abstract: In a FinFET integrated circuit, the fins are formed with a body thickness in the body area and then thickened in the source/drain area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the gates are covered by a composite gate cover layer to prevent thickening of the gates, which may short the gate to the source/drain.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventor: Jochen C. Beintner