Abstract: A method and device are for monitoring electric components in a pick-and-place device for substrates. The underside of a pick-up is monitored by an optical scanner during the pick-up phase and during the placing phase of a component. A lift drive for the pick-up is provided with a position sensor that is linked with a control device. The scanner emits and receives a scanning beam oriented transversally to the direction of lift and is likewise coupled with the control device, thereby allowing monitoring of the underside of the pick-up in a direct time-related manner with the picking and placing of the component. The various lift positions are saved and compared when a threshold value of the received scanning beam is exceeded so that the inventive device also allows for a monitoring of the height of the component.

Abstract: Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

Abstract: A method of fabricating a semiconductor device, having a nitride/high-k material/nitride gate dielectric stack with good thermal stability which does not diffuse into a silicon substrate, a polysilicon gate, or a polysilicon-germanium gate when experiencing subsequent high temperature processes, involving: (a) providing a substrate; (b) initiating formation of the nitride/high-k material/nitride gate dielectric stack by depositing a first ultra-thin nitride film on the substrate; (c) depositing a high-k material, such as a thin metal film, on the first ultra-thin nitride film; (d) depositing a second ultra-thin nitride film on the high-k material, thereby forming a sandwich structure; (e) completing formation of the nitride/high-k material/nitride gate dielectric stack from the sandwich structure; and (f) completing fabrication of the semiconductor device.

Abstract: The present invention provides a fabrication method for a semiconductor structure having a partly filled trench, having the following steps: provision of a semiconductor structure (1, 5) having a trench (2); filling of the trench (2) with a filling (10) in such a way that the filling (10) projects above a surface (OF) of the semiconductor structure (1, 5) by a first height (h1), the filling (10) covering the trench (2) and the periphery (20) of the trench (2); planarization of the filling (10) in a first etching step in such a way that the filling (10) is essentially planar with the surface (OF) of the semiconductor structure (1, 5); and sinking of the filling (10) in the trench (2) in a second etching step by a predetermined depth (T) proceeding from the surface of the semiconductor structure (1, 5); essentially the same plasma power and the same etchant composition being used for the first and second etching steps.

Abstract: A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

Abstract: A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing an interface of the silicon comprising layer of silicon-on-insulator circuitry with the insulator layer of the silicon-on-insulator circuitry. After the nitridizing, a field effect transistor gate is formed operably proximate the silicon comprising layer. Other methods, are disclosed. Integrated circuitry is contemplated regardless of the method of fabrication.

Abstract: The present invention relates to a method for the production of semiconductor components. This method comprises the steps of applying masking layers and components on epitaxial semiconductor substrates within the epitaxy reactor without removal of the substrate from the reactor. The masking layers may be HF soluble such that a gas etchant may be introduced within the reactor so as to etch a select number and portion of masking layers. This method may be used for production of lateral integrated components on a substrate wherein the components may be of the same or different type. Such types include electronic and optoelectronic components. Numerous masking layers may be applied, each defining particular windows intended to receive each of the various components. In the reactor, the masks may be selectively removed, then the components grown in the newly exposed windows.

Abstract: A semiconductor device comprises a substantially flat interconnection substrate having an interconnection pattern formed on a surface thereof. A semiconductor element is mounted on the substantially flat interconnection substrate so that an electrode terminal of the semiconductor element is electrically connected to the interconnection pattern. A heat radiation plate is formed in a form of a sheet having a concave portion so as to cover the semiconductor element and is bonded on the surface of the substantially flat interconnection substrate. An external connection terminal is formed on the other surface of the substantially flat interconnection substrate so as to penetrate through the substantially flat interconnection substrate and be electrically connected to the interconnection pattern. The heat radiation plate is formed of a heat-resistant resin containing carbon fibers.

Abstract: A test pattern (100, 200, 300, 400, 600, 700) has a first metal structure (102) disposed on a substrate (352), one or more intermediate layers (358) disposed above the first metal structure (102) and a second metal structure (104) disposed above the one or more intermediate layers (352). A first via (106) passes through the intermediate layers (352) and connects the first metal structure (102) to the second metal structure (104). One or more third metal structures (108) are disposed above the one or more intermediate layers (352) and the first metal structure (102). One or more second vias (110) pass through the intermediate layers (352) and connect the first metal structure (102) to the third metal structures (108). The second vias (110) are located outside of a radius (R) from a center of the first via (106). The third metal structures (110) are separated from the second metal structure (104) by a dielectric material (366).

Abstract: A gas analyzer for a semiconductor treater improved to be capable of monitoring leakage or change of gas composition influencing treatability of the semiconductor treater in situ is provided. A duct is provided on the outer wall of a chamber of the semiconductor treater for taking out gas to be analyzed from the chamber. A gas analytic chamber stores the gas to be analyzed taken out through the duct. A discharge formation part is mounted in the vicinity of the gas analytic chamber. The discharge formation part includes a high frequency generation coil generating a high frequency and forming a plasma of the gas to be analyzed in the gas analytic chamber. This gas analyzer further comprises a spectrometer analyzing the emission wavelength of the plasma of the gas to be analyzed.

Abstract: There is provided a method of fabricating a thin-film semiconductor device, including the steps of (a) melting and recrystallizing at least a surface of a thin semiconductor film formed on a substrate, in a pressure lower than an atmospheric pressure or in inert gas atmosphere, (b) keeping the substrate in atmosphere including oxygen gas, and (c) forming an insulating film on the thin semiconductor film with the substrate being kept in a pressure lower than an atmospheric pressure or inert gas atmosphere.

Abstract: An electro-optic device such as a smectic liquid crystal cell 1 with an active semiconductor backplane 3 is mounted on a hybrid substrate 2, for example of alumina or silica. Other active or passive electronic or optical components may also be mounted on the substrate, and interconnected by conductive tracks, for example by wire bonding 17, and the substrate itself may be mounted on a printed circuit board. The substrate may comprise a heat sink. The arrangement facilitates the safe connection of the liquid crystal cell and good optical alignment thereof.

Abstract: A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.

Abstract: An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

Abstract: On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

Abstract: The present invention provides a fabricating process for forming a flexible substrate, including the steps of: providing the substrate which is composed of a top plate and a bottom plate, and then a positive electrode layer and a organic electro-luminescence (EL) are formed in sequence on the bottom plate; after that, a same axial downward patterned template is pressed onto the bottom plate for “micro-patterning”, and thus the positive electrode layer and the organic electro-luminescence (EL) layer on the bottom plate are patterned in the same axial; providing a top plate, on which a metal layer as a negative electrode is formed; similarly, a same axial upper patterned template is pressed onto the top plate for “micro-patterning”, and thus the metal layer on the top plate is patterned in the same axial; finally, superimposing the top plate on the bottom plate so that the axis of patterned positive electrode layer and patterned organic EL layer crisscross with the axis of patterned metal layer to construct a c

Abstract: A ladder-type gate structure for a silicon-on-insulator (SOI) four-terminal semiconductor device is disclosed. The structure includes a gate having a first and second portion, a body region, which is under the first portion of the gate, a body contact, which is adjacent to the second portion of the gate, and a plurality of body contacts connecting the body region to the body contact through a drain region. The gate structure provides an independently controlled body region and includes a substantially uniform voltage across the body region in the SOI semiconductor device.

Abstract: A method of fabricating an electric circuit, including first and second working processes of performing respective first and second working operations on a circuit substrate, where3in the first working process includes a first substrate-identifying step of obtaining substrate identifying information identifying the substrate on which the first working operation is to be performed, a specific-information obtaining step of recognizing a specific-information providing portion of the substrate, to obtain specific information indicating at least one specific characteristic of the substrate, a first working step of performing the first working operation on the basis of the obtained specific information, and a specific-information storing step of storing the specific information in relation to the substrate identifying information, and the second working process includes a second substrate-identifying step of obtaining the substrate identifying information identifying the substrate on which the second working operat

Abstract: A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop.