Abstract: An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

Abstract: Techniques for selecting and utilizing one or more novel symbol structures, control signaling, and scheduling for wireless signal transmission/reception are presented. An example method is presented that includes determining (302), based on control information corresponding to a slot, that a user equipment (UE) (102A) or another UE (102B) in communication with a network node (106) is to transmit acknowledgement (ACK) or negative acknowledgement (NACK) feedback in the slot for a downlink signal received by the UE (102A) or the other UE (102B) in the slot. In addition, the example method includes transmitting (304) an intermediate uplink signal to the network node (106) and/or receiving an intermediate downlink signal from the network node (106) after the downlink signal is fully received and before transmission of the ACK or NACK feedback begins. Example apparatuses, such as UEs and network nodes, and computer programs/code are also presented.

Abstract: Polar codes may be generated with a variable block length utilizing puncturing. Some puncturing schemes consider punctured bits as unknown bits, and set the log likelihood ratio (LLR) for those bits to zero; while other puncturing schemes consider punctured bits as known bits, and set the LLR for those bits to infinity. Each of these puncturing schemes has been observed to provide benefits over the other under different circumstances, especially corresponding to different coding rates or different signal to noise ratio (SNR). According to aspects of the present disclosure, both puncturing schemes are compared, and the puncturing scheme resulting in the better performance is utilized for transmission.

Abstract: A network that supports retransmissions with fixed and minimum delays includes at least first, second and third transceivers. The first transceiver transmits to the second transceiver packets comprising data of first and second data types. The second transceiver: stores the received data in a second buffer; transmits to the third transceiver, without waiting a fixed delay, successfully-received packets comprising data of the first data type, which is encoded with a first error resistance level; and transmits to the third transceiver, after waiting the fixed delay, successfully-received packets comprising data of the second data type, which is also encoded with the first error resistance level. When the second transceiver receives a retransmission request from the third transceiver, it retransmits a packet comprising data of either the first or second data types, encoded with a second error resistance level that is higher than the first error resistance level.

Abstract: A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.

Abstract: Disclosed herein is a memory device and a method of descrambling and decoding encoded data. In one aspect, encoded data is received. A scrambling seed is obtained from the encoded data prior to decoding the encoded data. The encoded data is descrambled according to the scrambling seed, and the descrambled data is decoded. The descrambled data may be decoded according to statistics of the descrambled data.

Abstract: Optimizing error correcting code (ECC) in three-dimensional (3D) stacked memory including selecting, as an ECC memory chip, a memory chip of a plurality of memory chips in a 3D stacked memory structure, wherein the 3D stacked memory structure comprises the plurality of memory chips stacked vertically and coupled together using through-silicon vias; determining that an error has been detected in one of the plurality of memory chips in the 3D stacked memory structure; selecting, based on the detected error, an order of an ECC decoder of the ECC stored in the ECC memory chip; and correcting the detected error in the 3D stacked memory structure using the ECC stored in the ECC memory chip.

Abstract: A radio transmitter comprises transmitting circuitry and processing circuitry. The transmitting circuitry broadcasts a frequency modulation (FM) in-band on-channel (IBOC) radio signal, wherein the FM IBOC radio signal includes multiple subcarriers grouped into multiple frequency partitions. The processing circuitry is configured to receive input bits for transmitting; encode and puncture the input bits using forward error correction (FEC) encoding; distribute encoded input bits between a main encoded component and a backup encoded component, wherein encoded bits of the backup encoded component are delayed for a specified duration relative to encoded bits of the main encoded component; allocate the encoded input bits of the main and backup encoded components into frequency diverse sidebands of the FM IBOC radio signal; and modulate the encoded input bits for transmitting using the frequency diverse sidebands of the FM IBOC radio signal, wherein the modulation is a type of quadrature amplitude modulation (QAM).

Abstract: Although a distributed storage device can recover data from multiple failures this process produces excessive inter-zone network traffic when a chunk with user data is deleted. This disclosure employs an un-encoding erasure coding and partial coding chunks to facilitate data deletes while reducing inter-zone network traffic. Therefore a data chunk representative of partitioned disk space associated with a first zone of a data store can be determined to be marked for deletion. Consequently, the data chunk can be copied, resulting in a copied data chunk, to a second zone of the data store associated with a coding chunk comprising the data chunk. Based on the copied data chunk and the coding chunk, a partial coding chunk can be generated via un-encoding, wherein the partial coding chunk is a subset of the coding chunk.

Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.

Abstract: The described technology is generally directed towards reporting channel quality information from a wireless user equipment to the network, in a channel state information report that includes channel quality information based on a block error rate threshold value that corresponds to an ultra-reliable low latency communication when the user equipment is in the ultra-reliable low latency communication mode. The channel quality information corresponding to the ultra-reliable low latency communication mode block error rate threshold and the channel quality information corresponding to the enhanced mobile broadband mode block error rate threshold can be included in the same report. Alternatively, the user equipment is instructed to report either the channel quality information for-reliable low latency communication or for enhanced mobile broadband in the channel state information report.

Abstract: A method and system to surreptitiously inject data into a data stream over a communication channel including an error correction encoder circuit to apply an error correction scheme to a data stream to create an unfaulted data, a binary to bit value positioner that converts bits in confidential data to corresponding position value of bits in a packet, and a data stream encoder that flips a bit in the unfaulted data based on the binary to bit value positioner to create a bit-faulted data.

Abstract: A serial general purpose input/output system includes a transmitter, a cable, a receiver and a verification unit. The transmitter includes an encoder to perform cyclic redundancy check coding on a data to generate a cyclic redundancy check code for verifying the accuracy of the data, and a first serial general purpose input/output connector coupled to the encoder to transmit the data and the cyclic redundancy check code. The receiver includes a second serial general purpose input/output connector coupled to the first serial general purpose input/output connector by the serial general purpose input/output cable to receive the data and the cyclic redundancy check code from the first serial general purpose input/output connector.

Abstract: A polar code encoding and decoding method includes generating a first and second sub-codewords. The sub-codewords correspond to pre-codewords, and the pre-codewords have a shared data aspect. The sub-codewords provide useful error-recovery for data stored in a memory. When data is read from the memory, decoding takes place. The data read operation may include hard decision decoding, soft decision decoding, or hard decision decoding followed by soft decision decoding. In the method, the shared data aspect is used to decode a first sub-codeword for which decoding was not initially successful. An apparatus is also provided.

Abstract: Provided are a multi-channel package capable of reducing a test cost while performing a test at a high speed, and a test apparatus and a test method of testing the multi-channel package. The multi-channel package includes: a package substrate; and at least two semiconductor chips mounted on the package substrate and having different channels, wherein each of the at least two semiconductor chips includes a built-in-self-test (BIST) circuit and operates in one of a self-test mode, a tester mode, and a target mode during a test, and in the tester mode or the target mode, the at least two semiconductor chips are configured to be inter-channel cross-tested through an external signal path of the package substrate.

Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.

Abstract: A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

Abstract: A memory system includes: a memory device that includes a plurality of memory blocks each of which includes a plurality of pages that store data; and a controller suitable for performing command operations corresponding to a plurality of commands received from a host on the memory blocks, detecting performance results of the command operations performed on the memory blocks, detecting, among the memory blocks, first memory blocks where performance of the command operations failed as bad blocks, and copying and storing valid data in the first memory blocks in second memory blocks of the memory blocks.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.