Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

Abstract: Wireless communications systems and methods are introduced. A wireless communication device may arrange a first encoded information block including a first sub-block having a first bit location and a second sub-block having a second bit location. The second bit location is after the first bit location. The wireless communication device may also position the first location earlier in a decoding order of a receiving second wireless communication than the second bit location. The wireless communication device may transmit the first and second sub-blocks as an encoded information block to the second wireless communication device.

Abstract: A non-volatile (NV) memory accessing method using data protection with aid of look-ahead processing, and associated apparatus such as memory device, controller and encoding circuit thereof are provided. The NV memory accessing method may include: receiving a write command and data from a host device; obtaining at least one portion of data to be a plurality of messages, to generate a plurality of parity codes through look-ahead type encoding, wherein regarding a message: starting encoding a first partial message to generate a first encoded result; applying predetermined input response information to a second partial message to generate a second encoded result, and combining the first and the second encoded results to generate a first partial parity code; and starting encoding the message to generate a second partial parity code, and outputting the first and the second partial parity codes to generate a parity code; and writing into the NV memory.

Abstract: There is provided a method of obtaining one or more parity symbols (PS) of an encoding of information symbols (IS) according to a linear cyclic code, the method comprising: upon a permutation of information symbols (IS), generating data indicative of parity coefficients of a row of a generator matrix associated with the linear cyclic code, computing, for each given parity coefficient, a first data in accordance with, at least, the given parity coefficient and the first IS; updating, by the processing circuitry, for each given parity coefficient of the one or more parity coefficients, the first data, in accordance with, at least, the given parity coefficient and the respective IS; and upon meeting a parity completion criterion for a given parity coefficient, deriving a parity symbol from the respective first data, thereby obtaining the one or more parity symbols of the codeword of the linear cyclic code.

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

Abstract: A method includes receiving, by a computing entity of a dispersed storage network (DSN), a request from a requesting device of the DSN to perform an encoded data slice operation. The request includes an indication that the encoded data slice operation is a stage in a predefined DSN workflow. The method further includes sending, by the computing entity, a response to the requesting device that includes a DSN workflow tag, wherein the DSN workflow tag includes an identifier of the stage in the predefined DSN workflow. The method further includes enabling a performance optimization mode. The performance optimization mode includes one or more performance optimization procedures for one or more of: the stage and one or more future stages of the predefined DSN workflow. The method further includes executing the encoded data slice operation in accordance with the performance optimization mode.

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

Abstract: A memory device is provided. The memory device includes a memory array including a plurality of sections, and an inter-hamming difference analyzer. Each of the sections has an individual location in the memory array. The inter-hamming difference analyzer is configured to obtain a plurality of inter-hamming differences according to the number of unlike bits between content of each section of the plurality of sections corresponding to a first operating condition and content of another section of the plurality of sections corresponding to a second operating condition.

Abstract: A device and method for receiving communications with dynamic data correction, the method including receiving at a receiving device a data packet from a sending device, the data packet including a header, and a data payload including one or more message blocks and corresponding redundancy blocks; recognizing, via pre-configuration of the receiving device, that there are redundancy blocks to receive along with the one or more message blocks and reading in the message blocks and corresponding redundancy blocks; determining that at least one of the message blocks is defective (e.g., corrupt, missing, etc.); processing one or more of the redundancy blocks to correct the defective message blocks; and optionally sending a response message to the sending device. The method may further include identifying which message blocks are defective and sending a request for, and receiving, redundancy blocks corresponding to the identified defective message blocks.

Abstract: Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

Abstract: A memory device includes a plurality of memory cell arrays, a plurality of data transmitters corresponding to the plurality of memory cell arrays, respectively, and suitable for transmitting data read in parallel from the corresponding memory cell arrays, and a test circuit suitable for selecting one data transmitter among the plurality of data transmitters, and sequentially outputting data transmitted in parallel from the selected data transmitter to one data input/output pad among a plurality of data input/output pads, during a test mode.

Abstract: To ensure that there is an elected manager among storage nodes of an erasure coding group (“ECG”), an ECG manager (“ECGM”) election process is periodically performed among available storage nodes that are configured with the software to perform the services of an ECGM. When a storage node is activated, an ECGM process of the storage node begins executing and is assigned a process identifier (“PID”). A storage node can utilize a service query framework to identify other available storage nodes and retrieve their ECGM PIDs. The storage node then selects a PID according to a criterion and elects the storage node corresponding to the selected PID to be the acting ECGM. This process is performed periodically, so even if the acting ECGM storage node fails, a new ECGM is eventually selected from the available storage nodes.

Abstract: The present disclosure relates to a data transmission apparatus and a data transmission method, a reception. device and a reception. method, a program, and a data transmission system capable of surely switching transmission systems. A transmission unit capable of transmitting data by switching the plurality of transmission systems transmits a switching command for instructing to switch the transmission system. Then, as a measure against an error generated when the switching command is generated, an error correction code for correcting the error generated in the switching command is transmitted or it is confirmed whether the switching command has been successfully received or reception of the switching command has failed on the basis of the result of error detection relative to the transmitted switching command. The present technology is applied to, for example, a bus IF.

Abstract: Systems and methods are disclosed for decoding data. A first block of data may be obtained from a storage medium or received from a computing device. The first block of data includes a first codeword generated based on an error correction code. A first set of likelihood values is obtained from a neural network. The first set of likelihood values indicates probabilities that the first codeword will be decoded into one of a plurality of decoded values. A second set of likelihood values is obtained from a decoder based on the first block of data. The second set of likelihood values indicates probabilities that the first codeword will be decoded into one of the plurality of decoded values. The first codeword is decoded to obtain a decoded value based on the first set of likelihood values and the second set of likelihood values.

Abstract: To efficiently recover from a multiple storage node failure, a storage node concurrently restores data fragments to the multiple failed storage nodes, as opposed to restoring each node individually. In the VCS based storage technique, storage nodes are restored as part of an ECG repair process. For each ECG being repaired, a storage node performing the restoration process reads data fragments from active nodes in the ECG and generates new data fragments to replace any lost data fragments. The node then stores one of the new data fragments across each of the failed storage nodes. By concurrently restoring data fragments to each failed storage node, the data fragments needed to repair each ECG are only read once, thereby preserving disk operations and network bandwidth.

Abstract: A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2r).

Abstract: Disclosed are devices, systems and methods for error correction decoding using an iterative decoding scheme. An error correction circuit includes a node processor to perform a plurality of iterations for updating values of one or more variable nodes and one or more check nodes using initial values assigned to the one or more variable nodes, respectively, a trapping set detector to detect a trapping set in at least one of the plurality of iterations by applying a predetermined trapping set determination policy, and a post processor to reduce at least one of the initial values or invert at least one of values of the variable nodes corresponding to an iteration in which the trapping set is detected, upon detection of the trapping set.

Abstract: A computer-implemented method, according to one embodiment, includes: detecting that an error count resulting from reading a first page in a block of storage space in memory is above a first threshold, and reading a second page in the block of storage space. The second page is one which had a highest error count of the pages in the block of storage space following a last calibration of the block of storage space. Moreover, a determination is made as to whether an error count resulting from reading the second page is above the first threshold. In response to determining that the error count resulting from reading the second page is above the first threshold, the block of storage space is calibrated. Other systems, methods, and computer program products are described in additional embodiments.