Abstract: A method of receipt status reporting in a communication device (110), comprising configuring (S1) said communication device for periodic receipt status reporting by associating a first status report type with a value of a first reporting periodicity parameter and associating a second status report type with a value of second reporting periodicity parameter, said first status report type being different from said second status report type and said first reporting periodicity parameter being different from said second reporting periodicity parameter, and periodically (S2) sending receipt status reports of said first type according to said associated value of said first reporting periodicity parameter and receipt status reports of said second type according to said associated value of said second reporting periodicity parameter.

Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Abstract: Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.

Abstract: A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Abstract: A memory controller includes: a read operation controller for controlling the plurality of memory devices to perform read operation on a plurality of pages included in one stripe; an over-sampling read voltage determiner for determining over-sampling read voltages, based on soft read data of a selected page among at least two pages, when read operations on the at least two pages among the plurality of pages fail; an error bit recovery for recovering error estimation bits included in read data of the selected page, based on an over-sampling read data of the selected page, which is acquired using the over-sampling read voltages; and an error corrector for performing error correction decoding on conversion data obtained by recovering the error estimation bits included in the read data of the selected page. The plurality of pages included in one stripe is included in different memory devices among the plurality of memory devices.

Abstract: The present invention provides a decoding method of a flash memory controller, wherein the decoding method includes the steps of: reading first data from a flash memory module; decoding the first data, and recording at least one specific address of the flash memory module according to decoding results of the first data, wherein said at least one specific address corresponds to a bit having high reliability errors (HRE) of the first data; reading second data from the flash memory module; and decoding the second data according to said at least one specific address.

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract: Technology is disclosed for storing data in a distributed storage system using a virtual chunk service (VCS). In the VCS based storage technique, a storage node (“node”) is split into multiple VCSs and each of the VCSs can be assigned a unique ID in the distributed storage. A set of VCSs from a set of nodes form a storage group, which also can be assigned a unique ID in the distributed storage. When a data object is received for storage, a storage group is identified for the data object, the data object is encoded to generate multiple fragments and each fragment is stored in a VCS of the identified storage group. The data recovery process is made more efficient by using metadata, e.g., VCS to storage node mapping, storage group to VCS mapping, VCS to objects mapping, which eliminates resource intensive read and write operations during recovery.

Abstract: The present disclosure relates to polar encoding methods and apparatus. One example method includes obtaining locations of information bits and frozen bits based on a reliability order of polar channels, where reliability of a polar channel corresponding to the information bits is higher than reliability of a polar channel corresponding to the frozen bits, performing cyclic redundancy check (CRC) encoding on an information block, mapping bits obtained after the CRC encoding to the information bits, determining at least one bit of the frozen bits as a check frozen bit, where a value of the check frozen bit is determined based on values of P information bits that are in information bits prior to the check frozen bit and that meet a preset condition, and performing polar encoding on the information bits, the check frozen bit, and a frozen bit other than the check frozen bit.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks; and a controller suitable for checking a read operation time, a read level class, an error occurrence, and an error occurrence class when performing the read operation on each of the memory blocks, classifying the memory blocks into various classes based on a result of the checking, and differently setting a durability parameter for each of the memory blocks based on a result of the classifying of the memory blocks.

Abstract: An apparatus may include a circuit configured to receive an input signal at an input and process the input signal using a set of channel parameters. The circuit may further determine an error metric for the processing of the input signal using the set of channel parameters, compare the error metric to a plurality of thresholds, and when the error metric matches one of the plurality of thresholds, adapt, using an adaptation algorithm, the set of channel parameters to produce an updated set of channel parameters for use by the circuit as the set of channel parameters in subsequent processing of the input signal, the adaptation of the set of channel parameters being based on a weight corresponding to the matching threshold of the plurality of thresholds.

Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: A memory device including a self-test circuit, a memory cell array, a power voltage generator, and a redundant row address replacement circuit is provided. The self-test circuit is configured to generate a self-test data signal and a power voltage control signal. The memory cell array receives the self-test data signal and outputs a self-test failure signal. The power voltage generator generates a word line power voltage according to a power voltage control signal. The redundant row address replacement circuit receives the word line power voltage and the self-test failure signal to provide a redundant word line address to the memory cell array. The power voltage generator is configured to provide the word line power voltage in a built-in self-test (BIST) mode to be lower than the word line power voltage in a normal mode.

Abstract: A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.

Abstract: Methods and Apparatus are provided for downlink retransmission of Code Block Groups (CBGs) when CBG level ACK and NACK feedback is unreliable. A User Equipment (UE) transmits to a Base Station (BS) feedback indicating an Acknowledgement (ACK) or a Negative Acknowledgement (NACK) corresponding to each of received set of CBGs transmitted by the BS to the UE. The BS receives and decodes the feedback and transmits back to the UE information regarding a result of the decoding. The UE, based on the received information, determines whether the BS correctly received and decoded the ACK/NACK feedback, and in some cases, ACKs and NACKs corresponding to which CBGs were incorrectly decoded by the BS. The UE processes retransmitted CBGs received from the BS based on this determination.

Abstract: An IC includes testing circuitry including a Test Access Port (TAP) controller and Segment-Insertion-Bit circuits (SIBs) arranged in multiple hierarchy levels. Some of the SIBs are connected to hardware units, and some of the SIBs are root-SIBs that connect between neighbor hierarchy levels. A test bus runs in a daisy-chained loop path starting at the TAP controller, passing via at least some of the SIBs and ending at the TAP controller. Each root-SIB has an Open state and a Closed state. The TAP controller, for a selected subset of the hardware units that are to be tested, selects one or more root-SIBs that, when set to the Open state, make the selected subset of hardware units reachable by the test bus, and sends via the daisy-chained test bus a data stream comprising one or more instructions that set two or more of the selected root-SIBs to the Open state.

Abstract: An integrated circuit includes intellectual property (IP) processing circuitries each including a separate, respective at least one scan chain, and temperature management controller circuitry configured to transmit an input pattern including a plurality of bits to at least one scan chain of a first IP processing circuitry among the IP processing circuitries, detect a temperature of the first IP processing circuitries based on an output pattern received from the at least one scan chain in response to the input pattern being transmitted to the at least one scan chain of the first IP processing circuitry, and control at least one of an operation frequency or an operation voltage of the first IP processing circuitry based on the detected temperature of the first IP processing circuitry.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).