Abstract: Methods, systems, and devices for wireless communications are described. Some wireless communications systems may implement reliability thresholds for transmissions. Base stations and user equipment (UEs) may implement techniques to reduce coding rates in order to improve reliability. For example, a base station may dynamically indicate a UE-specific transport block size (TBS) scaling factor for communication. The base station may include an explicit TBS scaling factor indicator in a downlink transmission, an implicit indication of the TBS scaling factor based on an indicated mode of operation (for example, a repetition mode) for the UE, or a combination thereof. By dynamically selecting between different supported scaling factors, the wireless devices may implement TBS scaling factors that are non-proportional to resource scaling factors, resulting in lower coding rates.

Abstract: Various implementations described herein are directed to an integrated circuit having an array of bitcells. The integrated circuit may include latch circuitry having a latch for each row of bitcells that latches valid match data into the latch for each row of bitcells. The integrated circuit may include priority encoding circuitry that receives the valid match data from the latch for each row of bitcells. The integrated circuit may include first logic circuitry coupled between the array of bitcells and the priority encoding circuitry to assist with providing the valid match data to the latch circuitry.

Abstract: A variety of applications can include apparatus and/or methods that provide shared parity protection to data in memory devices of a memory system. Parity data of different data streams programmed into different blocks of one or more memory devices can be overlapped and wrapped into slots of a volatile memory arranged as a storage device for the parity data. A parity map of parity-to-data reflecting the overlapping of the parity data can be maintained in the volatile memory along with the overlapped parity. The parity map can be updated as parity data is generated from further programming of the data streams. The parity contents of the volatile memory, including the parity map, can be transferred to a non-volatile memory in response to a determination of an occurrence of a transfer criterion. The parity contents flushed to the non-volatile memory can be used to allow correct data reconstruction in case of failures in programming.

Abstract: An example apparatus includes an input buffer coupled to an input terminal, wherein the input buffer is configured to provide an input signal based on a voltage received at the input terminal, a test terminal configured to receive a probe signal, and a power supply terminal configured to receive an external supply voltage. The example apparatus further includes a test logic circuit configured to, in response to the probe signal indicating a test and an external supply voltage detection signal having a value indicating detection of the external supply voltage, initiate a probe contact detection test. During the initiate a probe contact detection test, the test logic circuit is configured to receive the input signal and to provide an output signal having a value based on the input signal.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

Abstract: A semiconductor device including scan configuration circuitry that reconfigures latches of the device into a scan chain in response to assertion of a scan enable control signal, and scan control circuitry including delay circuitry, scan enable circuitry, evaluation circuitry, and scan reset circuitry. The scan reset circuitry keeps each of the secure latches in a predetermined reset state until assertion of both an evaluation signal and a scan mode signal. The delay circuitry includes N series-coupled flip-flops selected from different cell libraries detecting assertion of the scan mode signal and asserting a delay output signal only after N transitions of a test clock. The scan enable circuitry asserts the scan enable control signal when a scan enable command signal and the delay output signal are both asserted. The evaluation circuitry asserts the evaluation signal only when a collective state of the delay circuitry has achieved a predetermined state.

Abstract: A method for monitoring communications between a device under test (DUT) and an automated test equipment (ATE) is disclosed. The method comprises programming an interface core and a protocol analyzer module onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test a DUT, wherein the interface core is operable to generate signals to communicate with the DUT using a protocol associated with the DUT. The method also comprises monitoring data and command traffic associated with the protocol in the interface core using the protocol analyzer module and storing results associated with the monitoring in a memory comprised within the protocol analyzer module. The method finally comprises transmitting the results upon request to an application program associated with the protocol analyzer module executing on the system controller.

Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

Abstract: Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.

Abstract: The disclosure discloses a method and device in UE and a base station for channel coding. A first node first determines a first bit block and then transmits a first radio signal, wherein bits of the first bit block are used to generate bits of a second bit block, a third bit block comprises bits of the second bit block and the first bit block, and the third bit block is used to generate the first radio signal. The first bit block, the second bit block and the third bit block comprise P1, P2 and P3 bits, respectively.

Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.

Abstract: The memory controller may include a command generator generating and outputting first and second read commands to a memory device so that respective first and second read operations are performed using a first read voltage, a calculator receiving first and second read data in response to the read commands, comparing the first and second read data each other, and calculating a number of first inverted cells and a number of second inverted cells based on a result of the comparing, each of the first inverted cells having a bit value that inverted from a first bit value to a second bit value, and each of the second inverted cells having a bit value that inverted from the second bit value to the first bit value, and a read voltage determiner changing the first read voltage depending on the number of first inverted cells and the number of second inverted cells.

Abstract: Described are fountain code constructs that solve multiple problems in distributed storage systems by providing systematic encoding, reduced repair locality, reduced encoding/decoding complexity, and enhanced reliability. Embodiments are suitable for the storage of large files and exhibit performance superior to existing codes, and demonstrate reduced implementation complexity and enhanced symbol repair locality.

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

Abstract: A storage device includes a nonvolatile memory including a plurality of nonvolatile memory cells, a write buffer memory storing first data and second data received from a host, and a storage controller storing the first data and the second data that are stored in the write buffer memory into the nonvolatile memory. The storage controller performs a first program operation and a second program operation on a plurality of first memory cells connected to a first word line group to store the first data, and performs a first program operation and a second program operation on a plurality of second memory cells connected to a second word line group to store the second data. While the storage controller performs the first program operation on the plurality of second memory cells, the first data is written in the write buffer memory.

Abstract: Filter information associated with a test to be performed with one or more memory components is determined. A set of memory components matching the filter information may be reserved for use in the testing. Test execution information defining a set of test processes of the test is determined. A connection with a first test process may be established and used to receive feedback information associated with execution of the test process. Based on the feedback information, a failure of the first test process may be identified.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.