Abstract: A method performed by a controller of a solid state drive (SSD) comprising receiving from a host a write request to store write data in a nonvolatile semiconductor storage device of the SSD. The method also comprises identifying a first codeword and a second codeword stored in the nonvolatile storage device, the first codeword and the second codeword configured to store write data corresponding to the write request. Responsive to the write request, the method comprises writing a first portion of the write data to the first codeword and writing a second portion of the write data to the second codeword, and sending a message to the host once the write data has been written to the nonvolatile semiconductor storage device. The first and second codewords are adjacently stored, and the write data has a length that is greater than the length of the first and second codewords.

Abstract: A method for sending communications with dynamic data correction to at least one receiving device includes dividing a message into one or more message blocks and determining corresponding redundancy blocks for the one or more message blocks, the redundancy blocks to be used by at least one of the receiving devices for message block detection or message block correction. The method further includes constructing a data packet including a header and a data payload including the one or more message blocks and the corresponding redundancy blocks. The construction of the data packet is such that it is processable by receiving devices that are configured to recognize and process the corresponding redundancy blocks and also processable by other receiving devices that cannot recognize the presence of the corresponding redundancy blocks. The method further includes sending the constructed data packet to the at least one receiving device.

Abstract: The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transfer rate beyond a 4G communication system, such as LTE. One embodiment of the present invention provides a method for channel encoding in a communication system, the method comprising: encoding second data, using an outer channel code; determining a value corresponding to first data; arranging the encoded second data in a block size unit corresponding to the second data, based on the determined value; and encoding the arranged second data, using an inner channel code.

Abstract: A method of testing a multiple power domain device includes sending a control signal from a test controller powered by a switchable power domain to a non-scan test data register powered by an always on power domain. The method further includes setting, using the control signal, a test data register value of the register to enable scan mode by bypassing an isolation cell between an output of the switchable domain and an input of the always on domain and, while the register value continuously enables scan mode: shifting a test pattern into a scan chain including a flip-flop coupled to the isolation cell, capturing a test result from the scan chain, and shifting the test pattern out of the scan chain to observe the test result. The isolation cell is configured to allow or disallow propagation of a signal from the output to the input.

Abstract: A system for testing memory includes logic that is configured to perform various normal memory operations (e.g., erase, read and write operations) on a memory device and to determine operational parameters associated with the memory operations. As an example, the amount of time to perform one or more memory operations may be measured, or a number of errors resulting from the memory operations may be counted or otherwise determined. One or more of the operational parameters may then be analyzed to determine whether they are in a range expected for counterfeit memory. If so, the logic determines that the memory under test is counterfeit (e.g., is recycled or counterfeit) and provides a notification about the authenticity of the memory. The logic may also estimate the age of the memory based on the operational parameters.

Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

Abstract: Methods, systems, and devices for methods for supporting mismatched transaction granularities are described. A memory system may include a host device the performs data transactions according to a first code word size that is different than a second code word size associated with a storage component within the memory system. A cache may be configured to receive, from the host device, a first code word associated of the first code word size and associated with a first address of the storage component. The cache may store the first code word. When the first code word is evicted from the cache, the memory system may generate a third code word of the second size based on the first code word and a second code word stored in the first address of the storage component and store the third code word at the first address of the storage component.

Abstract: Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.

Abstract: A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

Abstract: Embodiments of this application provide a polar code encoding and decoding method and apparatus. The method includes: obtaining an information bit set from a polar code construction sequence table based on an information bit length and a target code length of to-be-encoded information, where the polar code construction sequence table stores a mapping relationship between an encoding parameter and a construction sequence corresponding to the encoding parameter, the construction sequence is a sequence representing an order of reliability of polarized channels, and the encoding parameter includes at least one of an aggregation level, the target code length, and a mother code length, or the encoding parameter is a maximum mother code length; and performing polarization encoding on the to-be-encoded information based on the to-be-encoded information and the information bit set.

Abstract: A semiconductor memory device includes an ECC circuit; an error information register; a scrubbing control circuit to count refresh row addresses and output a scrubbing address for a scrubbing operation to be performed on at least one sub-page in a first memory cell row each time N refresh row addresses are counted; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword; and record the error information in the error information register and selectively determine, based on the error information, whether to write back a corrected first codeword in a memory location in which the data corresponding to the first codeword is stored.

Abstract: A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.

Abstract: A method of receipt status reporting in a communication device (110), comprising configuring (S1) said communication device for periodic receipt status reporting by associating a first status report type with a value of a first reporting periodicity parameter and associating a second status report type with a value of second reporting periodicity parameter, said first status report type being different from said second status report type and said first reporting periodicity parameter being different from said second reporting periodicity parameter, and periodically (S2) sending receipt status reports of said first type according to said associated value of said first reporting periodicity parameter and receipt status reports of said second type according to said associated value of said second reporting periodicity parameter.

Abstract: Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

Abstract: Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.

Abstract: A technique of extending a correction limit defined by an ECC is described. According to one aspect of the present invention, remaining errors that cannot be corrected by the ECCs in a data array is first identified and then formed in form of matrix with defined size. These remaining errors are flipped in value, namely from “1” to “0” or “0’ to “1” if the number of the errors are within a range or additional ECCs are applied to correct the errors in flipped data bits.

Abstract: A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Abstract: A memory controller includes: a read operation controller for controlling the plurality of memory devices to perform read operation on a plurality of pages included in one stripe; an over-sampling read voltage determiner for determining over-sampling read voltages, based on soft read data of a selected page among at least two pages, when read operations on the at least two pages among the plurality of pages fail; an error bit recovery for recovering error estimation bits included in read data of the selected page, based on an over-sampling read data of the selected page, which is acquired using the over-sampling read voltages; and an error corrector for performing error correction decoding on conversion data obtained by recovering the error estimation bits included in the read data of the selected page. The plurality of pages included in one stripe is included in different memory devices among the plurality of memory devices.