Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.

Abstract: An information handling system includes a memory manager that may detect corruption of a non-volatile random-access memory, and perform a recovery process of the non-volatile random-access memory that includes determining whether a header of the non-volatile random-access memory is corrupted. If the header is not corrupted, then a data region associated with the header may be recovered from recovery data values in a spare store in the non-volatile random-access memory. If the header is corrupted, then the header and the data region may be recovered from default data values.

Abstract: A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.

Abstract: The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.

Abstract: Providing for increased flexibility for large scale parity, the including: writing data to a storage system, including utilizing a first data protection scheme; identifying, for storage media in the storage system, characteristics of the storage media; identifying, in dependence up the characteristics for the storage media, a second data protection scheme to use for the data; and writing the data to the to the storage system utilizing the second data protection scheme.

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Abstract: A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

Abstract: An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

Abstract: Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

Abstract: Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

Abstract: A memory system includes a memory device including plural non-volatile memory blocks and a controller configured to determine whether a first memory block among the plural non-volatile memory blocks is re-usable after the first memory block is determined to be a bad block and copy second block information associated with a second memory block including a second program sequence number within a set range of a first program sequence number in the first memory block to first block information of the first memory block.

Abstract: Methods, systems, and devices for methods for supporting mismatched transaction granularities are described. A memory system may include a host device the performs data transactions according to a first code word size that is different than a second code word size associated with a storage component within the memory system. A cache may be configured to receive, from the host device, a first code word associated of the first code word size and associated with a first address of the storage component. The cache may store the first code word. When the first code word is evicted from the cache, the memory system may generate a third code word of the second size based on the first code word and a second code word stored in the first address of the storage component and store the third code word at the first address of the storage component.

Abstract: An Integrated Circuit (IC) includes a storage element and control circuitry. The control circuitry is configured to select, responsively to a scan-enable control, between a functional-data input and a scan-data input to serve as an input to the storage element, to selectively disable toggling of an output of the storage element, responsively to a clock-enable control, by gating a clock signal provided to the storage element, and, while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, to select the input of the storage element to be the scan-data input.

Abstract: Techniques are disclosed for software development on utility devices. In an example, a utility device, responsive to validating a manufacturer signature, transitions to an isolated development mode. When in the isolated development mode, the utility device is restricted from joining a network and receives an application from a development computing system. The utility device validates a network signature and transitions to a network testing mode. When in the network testing mode, the utility device joins the network, registers with a head end system via the network, and executes the application. After a threshold amount of time has lapsed the utility device transitions to the isolated development mode.

Abstract: A method of testing a slave device of an Inter-Integrated Circuit (I2C) bus is provided. The method includes the following steps: (A) starting a first read operation or a first write operation of the slave device, the first read operation or the first write operation including a sub-operation of sending a command, an acknowledgement signal, data, an address or a control byte to the slave device; (B) sending a start command or an end command to the slave device after or during the sub-operation; (C) after step (B), performing a second read operation or a second write operation on the slave device; and (D) after step (C), determining whether the second read operation or the second write operation is correctly performed.

Abstract: An information processing apparatus includes a processor, an information storage unit, a voltage supply unit, and a control unit. The information storage unit is configured to hold information indicating a voltage to be supplied to the processor. The voltage supply unit is configured to supply a predetermined voltage to the processor based on the information stored in the information storage unit. The control unit is configured to detect an alteration in software to be executed by the processor, and to make a setting for supplying a predetermined voltage to a power source unit based on the information stored in the information storage unit.

Abstract: A test coverage rate improvement system for pins of tested circuit board and a method thereof are disclosed. In the system, partial pins of a circuit board connector in a tested circuit board are not electrically connected to the boundary scan chip, test pins of the test pin board are pressed with the partial pins by a fixture of a boundary scan interconnect testing workstation to electrically connect the test pins to the partial pins. A test access port controller receives a detection signal for detecting the partial pins, which are not electrically connected to the boundary scan chip, of the circuit board connector through the test pin board from the test adapter card, and determines whether conduction is formed based on the detection signal, thereby achieving the technical effect of improving a test coverage rate for the pins of the tested circuit board.

Abstract: Embodiments herein describe a hardware based scrubbing scheme where correction logic is integrated with memory elements such that scrubbing is performed by hardware. The correction logic reads the data words stored in the memory element during idle cycles. If a correctable error is detected, the correction logic can then use a subsequent idle cycle to perform a write to correct the error (i.e., replace the corrupted data stored in the memory element with corrected data). By using built-in or integrated correction logic, the embodiments herein do not add extra work for the processor, or can work with applications that do not include a processor. Further, because the correction logic scrubs the memory during idle cycles, correcting bit errors does not have a negative impact on the performance of the memory element. Memory scrubbing can delay the degradation of data error, extending the integrity of the data in the memory.

Abstract: A memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The memory controller includes a monitor circuit to generate a monitor signal indicating at least one characteristic that varies based on a variation in a manufacturing process condition under which the memory controller was manufactured; a digitization circuit to digitize the monitor signal at a plurality of timings to generate a plurality of digitized monitor signals, each of the plurality of digitized monitor signals having a first size; and a compression circuit to compress the plurality of digitized monitor signals data into first data having the first size.

Abstract: One embodiment provides a system which facilitates organization of data. During operation, the system allocates, to a function associated with a host, a number of block columns to obtain a physical storage space for the function, wherein a block column corresponds to a block from each of a plurality of dies of a non-volatile storage device. In response to processing an incoming host write instruction and an internal background write instruction, the system allocates a first block column to the incoming host write instruction and a second block column to the internal background write instruction, thereby extending a lifespan of the non-volatile storage device by recycling the first block column when deleting a namespace or virtual machine associated with the function.