Patents Examined by John J. Tabone, Jr.
  • Error code calculation on sensing circuitry
    Patent number: 11340983
    Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Perry V. Lea, Timothy P. Finkbeiner
  • Memory block defect detection and management
    Patent number: 11340982
    Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Guang Hu, Ting Luo
  • Flexible test systems and methods
    Patent number: 11334459
    Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 17, 2022
    Assignee: Advantest Corporation
    Inventor: Michael Bautista
  • Scan wrapper architecture for system-on-chip
    Patent number: 11320485
    Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 3, 2022
    Assignee: NXP USA, Inc.
    Inventors: Akhil Garg, Sahil Jain
  • Programmable test compactor for improving defect determination
    Patent number: 11320487
    Abstract: A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: May 3, 2022
    Assignee: SIEMENS INDUSTRY SOFTWARE INC.
    Inventors: Wu-Tung Cheng, Chen Wang, Mark A. Kassab
  • Generation of polar codes with a variable block length utilizing puncturing
    Patent number: 11309997
    Abstract: Polar codes may be generated with a variable block length utilizing puncturing. Some puncturing schemes consider punctured bits as unknown bits, and set the log likelihood ratio (LLR) for those bits to zero; while other puncturing schemes consider punctured bits as known bits, and set the LLR for those bits to infinity. Each of these puncturing schemes has been observed to provide benefits over the other under different circumstances, especially corresponding to different coding rates or different signal to noise ratio (SNR). According to aspects of the present disclosure, both puncturing schemes are compared, and the puncturing scheme resulting in the better performance is utilized for transmission.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Jian Li, Jilei Hou, Neng Wang
  • Save and restore register
    Patent number: 11300614
    Abstract: A save and restore (SR) register system is disclosed. Some embodiments include a first memory state element (MSE), a second MSE, and a control circuit. The first MSE is configured to: clock in a first data value during a normal mode and hold the first data value during a first testing mode; and clock in a first test sequence during a second testing mode. The second MSE is configured to: clock in the first data value during the normal mode; and clock in a second test sequence during the first testing mode. The control circuit configured to: restore the second MSE to the first data value based on an output port of the first MSE after the second MSE clocks in the second test sequence; and restore the first MSE based on an output port of the second MSE after the first MSE clocks in the first test sequence.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: April 12, 2022
    Assignee: Synopsys, Inc.
    Inventor: Adam Cron
  • Test method and test system
    Patent number: 11293982
    Abstract: The present invention provides an improved testing of a complex device under test, in particular a parallel analysis of signals of a device under test. Multiple signals of the device under test may be acquired and characteristic parameters of the acquired signals may be determined. The determined characteristic parameters of the multiple signals may be stored. In particular, the characteristic parameters may be stored in form of an array, table or spread sheet.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 5, 2022
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Philip Diegmann
  • Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die
    Patent number: 11293979
    Abstract: The present invention provides a reliable method and arrangement for boundary scan testing and debugging newly manufactured multi-chip modules (MCMs) made to identical design specifications with no Known Good Die therein. Advantageously, a first and a second MCM are temporarily linked in tandem for boundary scan testing through a motherboard and daisy-chaining their internal dice, and interlinking the corresponding boundary scan cells of the identical dice of the first and second MCM to (1) run self-test on individual MCMs and mutual test on the MCMs connected in tandem in order to generate an extended Truth Table that includes responses from an array of combined netlists of the first and second MCMs, and (2) to diagnose mismatched bits in the extended Truth Table using a Boundary Scan Diagnostics software so as to identify defects in the first and second MCMs.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: April 5, 2022
    Inventor: Peter Shun Shen Wang
  • Method and system for validating a memory device
    Patent number: 11281530
    Abstract: The present invention relates to a method of validating a memory device. The method includes validating a second memory device based on one or more first microcode instructions stored in a validated predetermined part of a first memory device to detect the operational status of the second memory device. Further, the method includes receiving one or more second microcode instructions upon validating the second memory device. Finally, validating the first memory device based on the one or more second microcode instructions stored in the second memory device to detect the operational status of the first memory device.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rengaraja Sudarmani, Prathiksha Gautham, Uday Kumar N B, Abhinav Sharma, Sachin Suresh Upadhya
  • Memory embedded full scan for latent defects
    Patent number: 11280832
    Abstract: A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: March 22, 2022
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Frank David Frederick, Richard Slobodnik
  • Memory controller and flash memory system
    Patent number: 11275651
    Abstract: A memory controller includes a control circuit. The control circuit sets each block in a flash memory to an SLC mode or an MLC mode. The control circuit configures blocks set to the SLC mode into a first group. The control circuit configures blocks set to the MLC mode into a second group. The control circuit allocates the blocks constituting the first group to a first data block and a first redundant block. The control circuit allocates the blocks constituting the second group to a second data block and a second redundant block. The control circuit writes data required to be saved into the first data block. The control circuit writes first redundant data into the first redundant block. The control circuit writes replicated data of the data written into the first data block into the second data block. The control circuit writes second redundant data into the second redundant block.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: March 15, 2022
    Assignee: TDK CORPORATION
    Inventor: Kenichi Takubo
  • Programmable scan compression
    Patent number: 11275112
    Abstract: An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: March 15, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Bharat P. Londhe, Jay Shah, Aniruddha M. Bhasale
  • Semiconductor integrated circuit
    Patent number: 11262404
    Abstract: Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 1, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Hiromitsu Kimura
  • Semiconductor device
    Patent number: 11262403
    Abstract: According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: March 1, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuki Watanabe, Toshiaki Dozaka
  • Management of test resources to perform testing of memory components under different temperature conditions
    Patent number: 11257565
    Abstract: Filter information including a first temperature level and a second temperature level associated with a test process to be executed on one or more memory components is determined. Information associated with the test process is distributed to a first test component including a first set of memory components and a first temperature control component and a second test component including a second set of memory components and a second temperature control component. First feedback information associated with execution of the test process by the first test component at the first temperature level established by the first temperature control component is received. Second feedback information associated with execution of the test process by the second test component at the second temperature level established by the second temperature control component is received.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Daniel Scobee, Frederick Jensen
  • Power-collapsible boundary scan
    Patent number: 11249134
    Abstract: Physical or off-chip interfaces may be selectively bypassed in a boundary scan chain. A bypass control signal may be produced that indicates whether to bypass a selected one of the interfaces. In response to a first state of a bypass control signal, a multiplexer may couple the scan chain output of an interface boundary scan cell to the scan chain input of a successor boundary scan cell of the interface boundary scan cell. In response to a second state of the bypass control signal, the multiplexer may couple the scan chain output of a predecessor boundary scan cell of the interface boundary scan cell to the scan chain input of the successor boundary scan cell, bypassing the interface boundary scan cell.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jain, Todd Christopher Reynolds, Xinyi Chang, Anuj Gangan
  • Wafer scale testing using a 2 signal JTAG interface
    Patent number: 11243253
    Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Method and device in UE and base station for channel coding
    Patent number: 11245417
    Abstract: The disclosure discloses a method and device in UE and a base station for channel coding. A first node first determines a first bit block and then transmits a first radio signal, wherein bits of the first bit block are used to generate bits of a second bit block, a third bit block comprises bits of the second bit block and the first bit block, and the third bit block is used to generate the first radio signal. The first bit block, the second bit block and the third bit block comprise P1, P2 and P3 bits, respectively.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: February 8, 2022
    Assignee: SHANGHAI LANGBO COMMUNICATION TECHNOLOGY COMPANY LIMITED
    Inventor: Xiaobo Zhang
  • Memory system and operating method of the same
    Patent number: 11238951
    Abstract: A memory system includes: a memory device that includes a plurality of memory blocks each of which includes a plurality of pages that store data; and a controller suitable for performing command operations corresponding to a plurality of commands received from a host on the memory blocks, detecting performance results of the command operations performed on the memory blocks, detecting, among the memory blocks, first memory blocks where performance of the command operations failed as bad blocks, and copying and storing valid data in the first memory blocks in second memory blocks of the memory blocks.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee