Abstract: A hermetically sealed glass chip carrier includes an outer glass ring and an inner glass base in which leads to the inner glass base pass between the ring and the base, with the ring, base and leads being sealed together by melting the glass in the vicinity of the seal. In one embodiment, the base includes a stepped annular lip with the leads protruding between the space between the base and the lip and onto the top surface of the lip. In an alternative embodiment, a Kovar substrate pad may be secured to the base. Complete hermetic sealing is accomplished through the use of a lid which contacts the top surface of the ring and is hermetically sealed thereto. The external leads may be formed and trimmed in various configurations to provide an elevated pad, a plug-in, or a socket-type configuration.

Abstract: Solid-state overvoltage protection devices, preferably formed of deposited thin film, chalcogenide, threshold switching materials, typically include at least one elongated current conduction path through an elongated cross-sectional area of the threshold switching material. The cross-sectional area is formed with a length far exceeding the effective width thereof for distributing the transient current produced by overvoltage conditions over a relatively large area. In this manner, the concentration of localized heating effects can be avoided.

Abstract: A tunnel injection controlling type semiconductor device comprising a source semiconductor region having a certain conductivity type for supplying carriers, a drain semiconductor region for receiving the carriers, and a gate electrode for controlling the flow of these carriers. A highly-doped semiconductor region having a conductivity type opposite to that of the source semiconductor region is provided in contact with the source region or contained locally in the source region to cause tunnel injection of carriers. The potential level of this highly-doped region is varied by virtue of the static induction effect exerted by the voltage applied to the gate electrode which is provided at a site close to but separate from the highly-doped region, and to the drain semiconductor region.

Abstract: A bipolar transistor formed on the face of a semiconductor substrate which includes an extrinsic base of a first conductivity type formed in a portion of an emitter-base region of said semiconductor. A conducting base contacting layer is formed over the extrinsic base which has a non-conducting spacer formed over a sidewall thereof. An intrinsic base in the emitter-base region is juxtaposed to the extrinsic base. An emitter of a second conductivity type is formed within the intrinsic base with an edge of the emitter being aligned with an outer edge of the spacer.

Abstract: An integrated circuit device having signal electrodes, a common electrode, an other circuit elements, a glazing layer, an extension extending over the glazing layer from the common electrode, an insulating layer formed between the extension and the signal electrodes, and a diffusion preventing layer formed close to the glazing layer between the glazing layer and another layer.

Abstract: A multilayer data carrier into which a carrier element supporting an IC module is incorporated comprises a flexible substrate on which contact surfaces are formed which are connected to the IC module via leads. The carrier element is deformed in such a way, when being incorporated into the data carrier, that the IC module, in the finished data carrier, is located in the center of the card protected by cover layers of the card and the contact surfaces are flush with the surface of the card. A method for producing the data carrier comprises laminating a substrate layer carrying an IC-module with its leads and contact pad surfaces on one surface thereof between outer protective layers and with a central core layer such that the IC-module is disposed centrally within the data carrier with the contact surfaces disposed in apertures in one of the outer protective layers flush with the surface of said one layer.

Abstract: A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick film, and these films are provided in such a manner that the thin film is in contact with the upper side of the thick film (the relatively thick film is a first-level film, and the relatively thin film is a second-level film).

Abstract: This driver element for inductive loads, specifically DC motors, step motors, solenoids, and the like comprises a transistor bridge, each transistor of the bridge being parallel connected to a respective flyback diode ensuring recirculation of the current on switching the transistors off. The diodes are of the Schottky type, so as to ensure reduced switching loss and improved reliability of the element. The Schottky diodes are formed by leaving a non-diffused portion of the collector epitaxial layer through the base and emitter regions up to the device surface so as to contact the emitter metallization layer.

Abstract: A resistively stabilized transistor in which secondary breakdown is prevented by the insertion of a floating emitter protection region around only one end of a stabilizing resistive region. The transistor includes an ordinary emitter region located within a base region. A floating emitter region surrounds the ordinary emitter region. An elongated stabilizing resistive region has one end connected to the ordinary emitter region and the other to the base region. The protection region is positioned around, but spaced from, an end portion of the stabilizing resistive region only in the area where the resistive region connects to the ordinary emitter region.

Abstract: A modulation-doped field effect transistor comprises a gate recess through a top insulating layer, having a cross-section in a semiconductor layer increasing down to an interface with a further semiconductor layer and thereafter having a cross-section in the further semiconductor layer decreasing down to the bottom of the recess in the further semiconductor layer. A gate electrode is formed in the recess.

Abstract: The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.

Abstract: In a semiconductor integrated circuit having a double-layered wiring construction, wirings between adjacent logic function blocks of the circuit are provided using first level wirings of the double-layered wiring construction, and wirings among logic function blocks or between two logic function blocks having at least one intervening logic function block are provided by second level wirings of the double-layered wiring construction.

Abstract: A heterojunction transistor has an acceptor doped superlattice base of sub-micron thickness, a composite emitter with a donor concentration adjacent the base, with a wider bandgap energy than the base, and with a low recombination velocity to minimize minority carrier diffusion and to set the divergence of emitter and base carrier velocities, and a collector configured like the emitter, permitting control and optimization of the cut-in voltage. The method for making the transistor includes forming the base, emitter, and collector by non-compensated, non-planar wafer processing techniques.

Abstract: A lateral bipolar transistor affording a good controllability for a base length is disclosed.In fabricating a lateral bipolar transistor by forming a single crystal column and disposing heavily doped polycrystalline regions on both sides of the column, contact surfaces between the single crystal column and the heavily doped polycrystalline regions are controlled by etching of an oxide film. The etching of the oxide film can provide a device of a precision higher than attained by controlling any other element.

Abstract: Field effect transistors are provided and more particularly those which work at very high frequencies.According to the invention the field effect transistor has a vertical structure, comprising an access electrode, source or drain, on each of the two faces of the substrate wafer. The gate is formed by an N type epitaxial layer thickness sandwiched between two N.sup.+ type layers. The gate thickness is then limited by the epitaxial layer thickness which can be obtained of the order of a few hundred angstroms. The gate contact is taken by means of lateral metal layers, on the chamfered sides of the epitaxial layer.

Abstract: A two-terminal field effect transistor device which is capable of operation as an oscillator including a field effect transistor connected in a two-terminal manner. The transistor has the usual drain source and gate electrodes and oscillating instability is provided by means of an inductance means of value so as to provide this circuit instability to enable circuit oscillations. The two-terminal arrangement is enabled by means of essentially interconnecting the gate and drain electrodes by way of said inductance means.

Abstract: A MOS transistor is featured by providing mult-layered covering elements for covering a channel region of the semiconductor device. Each of the covering elements is interposed by an insulating layer. Preferably, the covering layers comprise first and second covering layers neither of which are connected to either of the drain electrode, the source electrode, or the gate electrode. A field plate layer, as a third covering layer, is disposed over the first and second covering layers.

Abstract: A MOS transistor is featured by the provision of a conductive covering element for covering a drift channel region of the semiconductor device. The covering element is interposed by an insulating layer which is relatively thick. The covering element comprises a floating conductive element, disposed on the insulating layer, and a field plate means, disposed on a second insulating layer.

Abstract: A semiconductor circuit apparatus including several semiconductor substrates interconnected by having elevated portions of one substrate contacting the surface of the second substrate where both substrates include at least one electrical circuit. Also included is a method for forming this three dimensional integrated circuit structure by forming the elevated portions of the semiconductor substrate by applying an orientation-dependent etch and then applying an electrically conductive coating to this elevated portion. Electrically conductive bonding pads are formed on the second semiconductor substrate. These pads are selectively positioned relative to the elevated portions formed on the first semiconductor substrate. Contacts between the first and second substrate are formed by forming bonds between the elevated portions on the one substrate and the electrically conductive pads on the second substrate.

Abstract: There is a conductivity modulated MOS transistor comprising: a p-type region formed in the surface area of an n.sup.- -type layer formed on a p.sup.+ -type layer; an n.sup.+ -type region formed in the surface area of this p-type region to face the n.sup.- -type layer; and a gate electrode formed through a gate insulation layer over a surface region of the p-type region sandwiched between the n.sup.- -type layer and the n.sup.+ -type region. This MOS transistor further comprises a p.sup.+ -type region formed inside the p-type region, at least under the n.sup.+ -type region and having a higher impurity concentration than the p-type region.