Abstract: A semiconductor device has a safety device which includes an improved lateral bipolar transistor structure. The improvement is obtained by incorporating an auxiliary field effect transistor which has the emitter as its source zone and the collector as its drain zone, and in which the threshold voltage of the auxiliary field effect transistor is lower than the avalanche breakdown voltage of the collector-base junction of the lateral transistor. As a result, the lateral transistor switches sooner, at a lower voltage, to the readily conductive on-state.

Abstract: A planar type thyristor has a semiconductor substrate of one conductivity type, a first and second regions of other conductivity type formed in the substrate and a third region of the one conductivity type formed in one of the first and second regions. An electrically floating electrode is formed on the substrate between the first and second region via an insulator film and a control electrode is formed on the floating electrode via another insulator film. A gate trigger current is controlled by a voltage applied to the control electrode.

Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.

Abstract: A temperature controller includes a temperature sensor mounted on a semiconductor device to be controlled in temperature, a temperature controlling assembly mounted on the semiconductor device and responsive to an output signal from the temperature sensor for controlling the temperature of the semiconductor device so as to be substantially constant, and a thermal insulation disposed around the semiconductor device and the temperature sensor in contact therewith. Since the temperature of the semiconductor device is directly detected by the temperature sensor, and directly controlled by the temperature controlling assembly, the temperature of the semiconductor device can be controlled quickly. The temperature of the semiconductor device can also be controlled highly accurately since the temperature sensor and the temperature controlling assembly are mounted directly on the semiconductor device and surrounded by the thermal insulation.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing approximate dopant materials into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.

Abstract: A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region.

Abstract: There is a conductivity modulated MOS transistor comprising: a p-type region formed in the surface area of an n.sup.- -type layer formed on a p.sup.+ -type layer; an n.sup.+ -type region formed in the surface area of this p-type region to face the n.sup.- -type layer; and a gate electrode formed through a gate insulation layer over a surface region of the p-type region sandwiched between the n.sup.- -type layer and the n.sup.+ -type region. This MOS transistor further comprises a p.sup.+ -type region formed inside the p-type region, at least under the n.sup.+ -type region and having a higher impurity concentration than the p-type region.

Abstract: A semiconductor component having bump-like, metallic lead contacts and multilayer wiring wherein individual tracks of each and every electrical signal or potential to be wired in multilayer wiring technology are electrically connected to the respective lead contact in the region thereof and to one another, but are separated from one another in the remaining regions of the semiconductor component by insulating layers. The various insulating layers terminate at different distances from the lead contacts in such fashion that their ends, depending upon the embodiment, form a funnel that tapers either down or up. The difference of the respective distance of the ends of two neighboring insulating layers from the corresponding lead contacts amounts to at least twice the thickness of one of the two layers. Given different layer thicknesses, a dimension of the thicker layer is used. An insulating layer may be at most 2 .mu.m thick, and preferably 1 .mu.m.

Abstract: Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a graded, buried spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur.

Abstract: Two-terminal active devices, such as IMPATT and Gunn diodes, are combined with passive devices in a monolithic form using a plated metal heat sink to support the active elements and a coated-on dielectric to support the passive elements. Impedance-matching circuitry is preferably placed very close to (or partially overlapping) the active device, thereby eliminating detrimental device-to-circuit transition losses.

Abstract: A power transistor structure that is well suited to both switching and lower-voltage linear applications is displayed. A key element of the design is thin-film ballast resistors that act as a second level of interconnect. They can be connected to or insulated from the overlying metal and the underlying silicon, except where contact holes are provided. Thus, an intricate structure having small emitters with individual ballast resistors can be fabricated below the wide metal busses required to carry current out of a large power array. The result is a ballasting scheme that can be optimized for a wide range of linear and switching applications while making efficient use of metallization which often limits the size of power arrays. This is especially important in the design of IC power transistors where both the emitter and collector current must be conducted out of the array with surface metallization.

Abstract: A semiconductor device which is provided with a surface channel type or bulk channel type MIS FET. The MIS FET comprises at least a semiconductor substrate of a first conductivity type, a layer member formed in a predetermined pattern on the major surface of the substrate and having an insulating side surface; an insulating layer formed on the major surface of the substrate to extend from the insulating side surface in a direction opposite from the layer member; a conductive layer formed on the major surface of the insulating layer in contact with the insulating side surface of the layer member; and a first semiconductor region of a second conductivity type formed in the semiconductor substrate having a marginal edge corresponding to that of the conductive layer.

Abstract: A semiconductor device includes a semiconductor body in which a field effect transistor is formed which is composed of a number of parallel-connected subtransistors. Each subtransistor comprises a polygonal box-shaped cell of the semiconductor body. These cells each comprise a first semiconductor zone embedded in the semiconductor body and a second semiconductor zone embedded in the first zone. The peripheral part of the semiconductor body surrounding the first zone serves as a drain zone of the subtransistor, while the second zone serves as a source zone and a narrow edge strip of the first zone lying between the second zone and the peripheral part serves as a channel zone. The peripheral part comprises strip-shaped parts which extend in the direction of a central part of the first zone. The transistor has a comparatively low resistance in the switched-on state.

Abstract: A thyristor is comprised of a main thyristor region, a gate region for causing the main thyristor region to be turned on in response to a gate signal, and an amplifying gate region which is turned on to permit the main thyristor region to be turned on when an overvoltage is supplied to the thyristor in the absence of gate signal at the gate portion. The amplifying gate region is provided in a region except an intermediate region between the gate portion and the end of the main thyristor region facing the gate portion. A minority carrier lifetime in the amplifying gate region is longer than that of the main thyristor region and the gate portion.

Abstract: An integrated circuit package for high density applications comprises spring contacts on one face thereof for its removable mounting onto a printed circuit board, the mounting being accomplished by means of a frame assembly and the package being automatically fabricable in a continuous flow process involving its assembly on a transport tape and its final cutting therefrom.

Abstract: A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped.

Abstract: An improved high frequency high power transistor assembly capable of delivering 600 watts or more at 100 MHz and higher without the need for water cooling is described. Four transistor die individually mounted on separate BeO ceramic isolators are installed in a recessed cavity in a copper base. The BeO isolators have metallized top surfaces which connect to the backside output contacts of the transistor die and extend toward the centerline of the cavity. They connect to a longitudally arranged input-output assembly centrally located over the center line of the cavity. The input-output assembly has a wrap-around electrode structure which brings the transistor output connections to the upper surface of the assembly for easy bonding to the output leads. The input to the individual die is via individual ballast resistors mounted on the input-output assembly, one per transistor, to provide transistor-to-transistor matching for more uniform current distribution.

Abstract: A new semiconductor power device, suitable for electrical switching in automotive applications, is proposed. This device combines the low specific on-resistance achievable with bipolar regenerative switching devices with the convenience of insulated gate control of not only turn-on but also turn-off. A device structure is presented that also includes a pinch resistance effect to more rapidly produce turn-off. The anode region of the device is electrically shorted to its contiguous N-type region.

Abstract: A new semiconductor power device, suitable for electrical switching in automotive applications, is proposed. This device combines the low specific on-resistance achievable with bipolar regenerative switching devices with the convenience of insulated gate control of not only turn-on but also turn-off. A device structure is presented that also includes a pinch resistance effect to more rapidly produce turn-off.