Abstract: A thyristor has a pair of opposite conductivity bases between and respectively adjacent to opposite conductivity emitters. An auxiliary emitter serves for internal current gain and is provided with an auxiliary emitter cathode. In order to meet the mutually-contradictory requirements for great stability against unintentional trigger operations and a high trigger sensitivity, the auxiliary emitter electrode is connected by way of a semiconductor switch to the base layer adjacent the auxiliary emitter for increasing the trigger sensitivity. The thyristor may be employed in situations in which a high di/dt stability and a high dU/dt stability is desired.

Abstract: A thyristor has an n-emitter provided with a cathode, a p-emitter provided with an anode, and two base layers respectively adjacent thereto. Further, an auxiliary emitter serves the purpose of internal current gain. High ignition sensitivity is strived for in addition to good stability. To this end, a connectible auxiliary emitter is provided next to the auxiliary emitter, forming a three-layer structure together with the base layers with a higher current transfer ratio for the charge carriers emitted by it than the auxiliary emitter. In order to produce a high ignition sensitivity, the connectible auxiliary emitter is conductively connected to the auxiliary emitter via a semiconductor switch. The area of employment comprises trigger-sensitive thyristors with high di/dt and dU/dt stability.

Abstract: A thyristor has a semiconductor body with an n-emitter provided with a cathode, a p-emitter provided with an anode, and two base layers respectively adjacent thereto. Mutually contridictory requirements for great stability against unintentional ignition operations and a high degree of trigger insensitivity are met as well as possible. To this end, a connectible n(p) emitter is provided laterally adjacent the n(p) emitter, the connectible n(p) emitter forming a three layer structure together with the two base layers with a higher current transfer ratio for the charge carriers emitted thereby than the n(p) emitter. For the purpose of producing a high degree of ignition insensitivity, the connectible n(p) emitter can be selectively connected to the n(p) emitter via a semiconductor switch. The area of use encompasses ignition-sensitive thyristors having a high dU/dt load requirement.

Abstract: A power transistor having a collector region lying in one principal surface of a semiconductor body, a base region surrounded with the collector region and an emitter region surrounded with the base region, wherein the emitter region includes a main transistor operation portion, a ballast resistance portion and an electrode connection portion, and wherein the part of the base region surrounding the ballast resistance portion is narrower than the part of the base region surrounding the electrode connection portion.

Abstract: An axial lead semiconductor device package is provided for use with non-planar semiconductor die. By using solders of predetermined strength, wetting and flow characteristics, melting temperature, shape, area, and thickness, reliable attachment of non-planar die to planar mounting surfaces is achieved.

Abstract: An integrated circuit package having a large number of external connections is assembled using two lead frames stacked one atop the other. The lead frames have complementary lead patterns which interdigitate to provide a very close lead spacing at the periphery of a semiconductor chip on which a complex integrated circuit is fabricated.

Abstract: An inverted polycide extrinsic base contact serves as a diffusion source, yet still has low resistivity and is readily etchable down to silicon by techniques useful in manufacturing integrated circuits. The extrinsic base contact layer is made up of a metal silicide (e.g. WSi.sub.2) with an overlying doped polysilicon layer with coextensive apertures through doped polysilicon and metal silicide layers defining the emitter and intrinsic base region.The extrinsic base region is formed by diffusing boron impurities from the p.sup.+ polysilicon layer through the silicide layer. The silicide layer is of a metal silicide such as tungsten silicide (WSi.sub.2). The polysilicon layer acts as a diffusion source, since appropriate dopants (e.g., boron) diffuse rapidly through the metal silicide. Both the top surface of the p.sup.+ polysilicon layer and the sidewall edges of the polysilicon and silicide layers are covered by an insulating layer (e.g. SiO.sub.

Abstract: A GTO thyristor stack comprises a pair of GTO thyristors in parallel connection and a pair of diodes in anti-parallel connection therewith. The elements in one of the GTO thyristor pair and the diode pair are located in the middle of the stack structure and sandwiched by the elements in the other with all the elements stacked in electrical connection. The stack structure is clamped by a pair of clamper members.

Abstract: A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

Abstract: A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.

Abstract: A MOS type semiconductor device formed on an insulating layer and having a substrate electrode. A first semiconductor layer for forming a MOS type element is formed on the insulating layer and has a substrate region where a channel is to be formed. To this substrate region is connected a second semiconductor layer which is thinner than the first semiconductor layer and which has the same conductivity type as that of the substrate region where the channel is to be formed.

Abstract: A variable circuit configuration in which each of a plurality of series connected devices is connected to a lead frame having a parallel circuit for such connected devices that can control the by-pass or use of all, some or none of the connected devices.

Abstract: A field-effect transistor having a gate consisting of a metallic plane projecting metallized wells of less than one micron in diameter through the channel layer downwards to the semiconductor substrate. They are formed by ion-beam etching. Metallization is performed by cathodic sputtering of a substance which forms a Schottky contact with the semiconductor. The wells are spaced at intervals of less than one micron so as to form a row and are joined together by means of a gate electrode.

Abstract: A microcircuit package and sealing method in which a non-organic coating is used to hermetically seal the microcircuit. The microcircuit is isolated and insulated in order to protect the microcircuit from the high temperature required to apply and cure a non-organic coating. The materials and methods used to isolate and insulate the microcircuit are chosen so that the thermal coefficients of the materials are complementary and thus form a highly reliable, durable seal, while also insulating the microcircuit during the process of applying the non-organic coating.

Abstract: A contact shim for insertion between an electrode internal contact member and a contact surface of a semiconductor element in a semiconductor device assembly. The shim has a generally continuous body (2) provided with a number of apertures (4, 5, 6, 7) having a land (1) or finger extending at least partially thereacross, preferably a land comprises a bar which bisects an aperture (4, 5, 6, 7). The apertures and bisecting lands may be used as visual guides in aligning the shim with reference marks on the contact surface of the semiconductor element and, the means of attaching the shim to the element may be applied to the lands in order that any distortion consequent upon attachment is confined to the lands leaving the body of the shim undistorted.

Abstract: A lead frame with parallel side members and parallel transverse members defining chip receiving areas along the frame, has a chip pad at each area. A support lead extends from each corner of the chip pad to corresponding conjunctions of side and transverse members. A U-shaped support bar extends between each adjacent pair of support leads, each support bar including spaced parallel leg portions connected at inner ends to the support leads and at the outer ends by a lead support portion. Leads extend from each lead support portion towards the chip pad. By this means the chip can be assembled to the pad and wire bonding between chip and leads carried out and the leads can be preformed or not, as desired, prior to encapsulation. After encapsulation, the lead support portions can be trimmed off but the encapsulated device is still held in the lead frame but the leads are electrically isolated from each other. Testing can be carried out while devices are still in the lead frame.

Abstract: Bidirectional thyristor or Triac, including a semiconductor body, first and second antiparallel-connected thyristor sections integrated in the semiconductor body, each of the thyristor sections having an anode side, a cathode side, an emitter zone on the cathode side, a base zone on the cathode side, an emitter zone on the anode side having a given conductivity type, and a base zone on the anode side, a field-effect transistor being integrated into the semiconductor body and having a control, a source, and a drain terminal defining a load path, the source terminal being connected to the emitter zone on the cathode side of the first thyristor section and the drain terminal being connected to the base zone on the anode side forming a connection through the load path of the field-effect transistor, an auxiliary zone having the given conductivity type of the emitter zone on the anode side of the second thyristor section, the auxiliary zone being disposed between the emitter zone on the cathode side of the first t

Abstract: A semiconductor device includes a semiconductor substrate having electrodes brazed thereto. The electrode is made of a Cu-C composite material in which carbon fibers are embedded in copper matrix. The carbon fibers are so disposed as to be in a ring-like shape or a loop shape substantially in parallel with a surface of the semiconductor substrate onto which the electrode is brazed. The carbon fibers disposed in an outer peripheral portion have a higher longitudinal elastic modulus than that of the carbon fibers positioned at a central portion of the electrode. The electrode thus has a thermal expansion coefficient approximating to that of the semiconductor substrate. Content of copper can be increased at the central portion of the electrode for attaining a high thermal conductivity.

Abstract: A gate-source structure and fabrication method for a surface-gate static induction transistor. The method requires only one masking step during fabrication, thereby eliminating or minimizing mask registration problems during fabrication of the devices. The method and the device are characterized by a two-step etching process which forms T-shaped gate windows in layers of polycrystalline silicon with different doping levels. The source region is formed during an annealing step from the layer with high doping level. During the annealing step, the gate regions are also formed from gate impurities implanted previously in the gate windows. The source structure and the gate structure are separated by a silicon dioxide protective layer.

Abstract: A field effect transistor device is constituted by a semiinsulating substrate consisting of a compound semiconductor, an N type semiconductor layer formed on the substrate, a plurality of P type semiconductor gate regions aligned along a straight line and extending through the semiconductor layer to reach the substrate, source and drain electrodes disposed on the semiconductor layer on the opposite sides of the drain regions, a gate electrode having an ohmic contact with the gate regions and having a Schottky contact with the semiconductor layer interposed between the gate regions. Two gate regions on the opposite ends of the array are in contact with the boundary region of the transistor.The field effect transistor device is useful for fabricating an integrated circuit and consumes less electric power. Further it reduces dispersion in the gate pinch off voltage and can be prepared at a high yield.