Abstract: A semiconductor integrated circuit device comprises a first circuit block for processing a first signal, a second circuit block for processing a second signal different in frequency and/or signal level from the first signal, a conductor layer representing a substantially zero a.c. impedance and formed on a portion of a semiconductor chip between the first and second circuit blocks, and an isolation region formed in the portion of the semiconductor chip, the conductor layer and the isolation region being connected to each other through at least one contact hole provided between the first and second circuit blocks to prevent the mutual interference between the first and second circuit blocks.

Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability.

Abstract: A new semiconductor power device, suitable for electrical switching in automotive applications, is proposed. This device combines the low specific on-resistance achievable with bipolar regenerative switching devices with the convenience of insulated gate control of not only turn-on but also turn-off. A device structure is presented that also includes a pinch resistance effect to more rapidly produce turn-off.

Abstract: An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.

Abstract: What is disclosed is a semiconductor apparatus comprises a semiconductor element, a pair of in-line electrode leads having a mounting island supporting the semiconductor element and a molded housing of resin compound. The electrode leads and mounting island are made of an alloy having a thermal expansion coefficient in the range of about 7.times.10.sup.-6 1/C.degree. to about 14.times.10.sup.-6 1/C.degree.. Thus, when the device is subjected to temperature variations, there is little warpage or cracking in the device.

Abstract: A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

Abstract: The edge of a conformal coating over a mesa is usable to define a shoulder in the vertical dimension of the mesa which in turn is used for positioning. Structures are provided that permit electrodes at precise locations along the length of a mesa. A vertical field effect transistor is set forth with a mesa serving as the channel and the gate electrode positioned at a shoulder formed by the edge dimension of a coating on the sides of the mesa.

Abstract: A field effect transistor is described incorporating a semiconductor layer over a layer or substrate of semi-insulating semiconductor material and a gate electrode which periodically passes through the semiconductor layer to the substrate to form a plurality of conducting bars in the semiconductor layer for transistor current and which at pinch-off confines the current interior of each conducting bar. The invention overcomes the problem of leakage current at pinch-off, thus improving the efficiency of the field effect transistor as a power amplifier.

Abstract: A semiconductor device encapsulated within a plastic housing facilitates attachment to a circuit board when a dip soldering process is used. Terminal leads from the semiconductor device extend outwardly through the walls of the housing and are arranged to provide a wetting surface for solder when a semiconductor device that is attached to a circuit board is immersed in a molten solder bath. In one embodiment of the invention, the terminal leads extend upwardly from adjacent the side walls of the housing to a location substantially adjacent the top surface of the housing. When the semiconductor device and circuit board are inverted to immerse the semiconductor device into the solder, the terminal lead acts as a wetting surface to allow solder to flow to the location at which the terminal abuts the circuit board. In another embodiment, the terminal leads extend along the side walls of the housing to a location adjacent the end walls of the housing.

Abstract: A thyristor packaging system utilizes structured metal, strain buffers to provide paths of high electrical and thermal conductivity from the anode and cathode of a thyristor to power conductors connected to the anode and the cathode, such strain buffers each comprising a bundle of substantially parallel, closely packed strands of metal wire.

Abstract: A high power high frequency field effect transistor is achieved with a vertical structure of gallium arsenide including a semi-insulating substrate, a conductive layer over the substrate, a narrow-central post having small metal gate electrodes on each side, metal drain electrodes on the conductive layer spaced from the central post and a metal source electrode supported on the central post. A deep channel around the post separates the metal drains, gates and source. Increased power is obtained from a cellular unit including two parallel source stripes, four gates and three drains. The drains are connected together by the conductive layer and a drain pad at one end, and the gates are connected at the other end by a gate pad on an outer region of the substrate. The gate connections to the pad are isolated from the conductive layer by a bridge over a space etched in the lower layer. A method for fabrication of this structure is also provided.

Abstract: A structure associating a high current NPN transistor with a PNP control transistor also able to withstand relatively high currents in an integrated circuit structure. This structure comprises an N.sup.+ type substrate overlaid by a P type epitaxied layer and a second N type epitaxied layer. The PNP transistor is disposed in the center of a region defined by two successive peripheral isolating walls. The NPN transistor is disposed in the annular zone. In this zone, the N.sup.+ substrate and the N layer are connected together by a buried N.sup.+ type layer locally short-circuiting the P type layer along a ring, thus isolating the central part of this layer at the level of the PNP transistor.

Abstract: A semiconductor device has a semiconductor substrate with a first insulating layer formed thereon. A first wiring includes a layer extending over the first insulating layer and a metallic film of refractory metal having high melting point disposed on the wiring layer. A contact hole is formed in the second insulating layer. Then, a second wiring, having the same material as the first wiring layer, is provided as an upper layer. The metallic film is removed inside the contact hole and the second wiring layer is directly connected to the first wiring layer. Aluminum, silicon, aluminum-silicon alloy, copper-aluminum alloy and the like can be used for the first and second wiring layers. The metallic film may be made of titanium, titanium nitride, molybdenum, tungsten, platinum, chromium or may be a composite film or alloy film of these metals. Further, alloys of above-mentioned high melting point materials may be used. The metallic film has the thickness of about 300 to 3,000 .ANG. and preferably, 500 to 1,500 .

Abstract: A semiconductor integrated circuit includes pouch-shaped (in sectional view) isolation regions made of dielectric material consisting of boron and phosphor doped silicate glass. A circuit component is formed in an active region surrounded by adjacent isolation regions. Each pouch-shaped (in sectional view) isolation region is made using an anisotropic etchant and an isotropic etchant successively. There is a method for manufacturing the above device with high integration density and high operating speed.

Abstract: A semiconductor device comprising a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a bonding pad formed on the first insulating layer, a conductive layer formed on the first insulating layer and adjacent to the bonding pad, and a second insulating layer formed to cover the conductive layer characterized in that the surface of the second insulating layer formed on and near the conductive layer is made at the same level as or lower than the surface of the bonding pad.

Abstract: A high power semiconductor heat sink assembly comprising a semiconductor slice or chip and a heat sink structure. The heat sink structure comprises two spaced apart thermally and electrically conductive plates of for example aluminum between which the slice or chip is clamped. A device such as an O-ring is sandwiched between the plates so as to extend around the slice or chip and define a sealed compartment within which the slice or chip is located. An electrically non-conductive thermally conductive material such as a resin comprising alumina fills the space between the plates outside the compartment.

Abstract: A high power semiconductor package having a unitary extruded metal housing which serves as an efficient thermal heat sink and which includes integral constituents for retaining an encapsulating material. The extruded housing has open sides and an open top to facilitate installation of the semiconductor die assemblies and associated electronic components and terminals prior to enclosure in a molded or otherwise formed encapsulant.

Abstract: A submicron conductor is formed by placing a metal member over an insulator both terminating at a common defined edge. An angularly deposited metal against the edge provides a broad metal conductor attached along the entire edge of a thin metal member which is positioned on the substrate on a narrow line with the width defined by the horizontal component of the angular deposition. A removal operation removes with respect to the vertical component of the angular deposition the excess angularly deposited metal and leaves a vertical, very narrow metal conductor having a horizontal metal over the dielectric in electrical and supporting contact along the entire length. The asymmetry of the conductor provides field effect transistor advantages.

Abstract: A metal interconnect structure for an integrated circuit with a layer of refractory metal over the structure to prevent formation of hillocks, thereby eliminating a hard anodization step. The refractory metal may be tantalum, titanium-tungsten alloys, hafnium, or other refractory metals which form insulating anodic oxides.

Abstract: Controlled semiconductor switch with a semiconductor body containing a thyristor structure having a first zone of first conductivity type embedded in coplanar relationship in a second zone of second conductivity type; also containing a third zone of the first conductivity type and a fourth zone of the second conductivity type; and further containing an MIS-FET integrated into the semiconductor body and having a source zone of the first conductivity type embedded in coplanar relationship in a zone of the second conductivity type; an insulating layer disposed on the surface of the semiconductor body, a control electrode lying on the insulating layer and covering a first channel zone operatively associated with the FET; and a cathode electrode on the semiconductor body, including the features that the zone of the second conductivity type of the MIS-FET is embedded in the third zone in coplanar relationship therewith and forms the first channel zone at the surface of the semiconductor body; the second zone of the