Patents Examined by John LaMont
  • Patent number: 4460915
    Abstract: A plastic package for radiation sensitive electrically programmable read-only memory devices is disclosed. A "slug" of ultraviolet transmissive material, such as fused quartz, sapphire, or other suitable material is bonded to the radiation sensitive surface of the semiconductor chip. The chip is wire bonded and die attached in the conventional manner, and is then encapsulated within a shell using existing epoxy techniques. The slug is shaped such that its upper surface is not covered during the encapsulating process, and thus ultraviolet radiation can penetrate through the slug and be diffused onto the chip thereby erasing the memory cells.
    Type: Grant
    Filed: December 28, 1981
    Date of Patent: July 17, 1984
    Assignee: Intel Corporation
    Inventor: Paul R. Engel
  • Patent number: 4458259
    Abstract: A gate-source structure and fabrication method for a static induction transistor. The method and the device are embodied by the epitaxial layer of, for example, high resistivity p-type semiconductor material grown on an epitaxial layer of high resistivity n-type semiconductor material. A silicon dioxide layer with source and gate windows is formed on the p-type epitaxial layer. Source grooves are formed in the p-type epitaxial layer at source window locations and the grooves are diffused with n-type impurities to form a diffusion region which extends to connect with the n-type epitaxial layer. Source and gate electrodes are formed in the source and gate windows.
    Type: Grant
    Filed: November 12, 1981
    Date of Patent: July 3, 1984
    Assignee: GTE Laboratories Incorporated
    Inventor: Adrian I. Cogan
  • Patent number: 4456918
    Abstract: A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.
    Type: Grant
    Filed: October 6, 1981
    Date of Patent: June 26, 1984
    Assignee: Harris Corporation
    Inventor: James D. Beasom
  • Patent number: 4446476
    Abstract: An integrated circuit containing a refractory metallic silicide beneath a field isolation region and in electrical contact with electrical conductive regions of active impurity dopants in a semiconductive substrate; and process for the fabrication thereof.
    Type: Grant
    Filed: June 30, 1981
    Date of Patent: May 1, 1984
    Assignee: International Business Machines Corporation
    Inventors: Randall D. Isaac, Tak H. Ning, Denny D. Tang
  • Patent number: 4445133
    Abstract: Disclosed is a semiconductor device comprising: a semiconductor body having a first semiconductor layer of the N conductivity type, second and third semiconductor layers of the P conductivity type, and first and second regions of the N conductivity type formed in the second semiconductor layer; a cathode electrode having first and second portions formed on the first semiconductor region; a gate electrode provided in the second semiconductor layer in opposition to the cathode electrode with the second semiconductor region interposed therebetween; an anode electrode provided on the third semiconductor layer; an auxiliary electrode consisting of two first portions and one second portion connected at ends respectively to the first portions, said first portions being formed on said second region and having free ends spaced from each other, and said second portion formed on said second layer and extending along the periphery of the first portion of said cathode electrode; and the second portion of the cathode elect
    Type: Grant
    Filed: August 20, 1981
    Date of Patent: April 24, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Youichi Araki, Toshio Ogawa
  • Patent number: 4442445
    Abstract: Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n.sup.+ -.pi.-p.sup.+ -.pi. structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.
    Type: Grant
    Filed: November 23, 1981
    Date of Patent: April 10, 1984
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Roger J. Malik, Thomas R. AuCoin
  • Patent number: 4437107
    Abstract: A self-igniting thyristor has a zener diode integral with the thyristor, which zener diode bridges the central junction of the thyristor and the breakdown voltage of which determines the breakover voltage of the thyristor. The breakdown voltage of the zener diode is determined by the field geometry in that part of the PN junction of the zener diode which is located near the surface of the semiconductor body, where the breakdown is arranged to take place. A conducting screen is arranged over said portion of the PN junction of the zener diode and is separated from the underlying portion of the surface of the semiconductor body by an insulating layer. The thyristor is provided with means for influencing the potential of the screen, which in turn influences the field geometry and thus the breakdown voltage of the zener diode and the breakover voltage of the thyristor.
    Type: Grant
    Filed: September 28, 1981
    Date of Patent: March 13, 1984
    Assignee: ASEA Aktiebolag
    Inventors: Per-Erik Jonsson, Per Svedberg