Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

Abstract: The present invention relates to a method for forming an organic EL element having at least one pixel type comprising at least three different layers including a hole injection layer (HIL), a hole transport layer (HTL) and an emission layer (EML), characterized in that the HIL, the HTL and the EML of at least one pixel type are obtained by depositing inks wherein the layers are annealed after said depositing steps in a first, second and third annealing step and the difference of the annealing temperature of the first and of the second annealing step is below 35° C., preferably below 30° C., more preferably below 25° C. and the annealing temperature of the third annealing step is no more than 5° C.

Abstract: Provided is a mask assembly including a mask sheet including a pattern part with at least one opening part, and a welding part connected to the pattern part, and a mask frame with the mask sheet mounted thereon and welded to the welding part. The mask sheet includes a first surface configured to fact the mask frame and a second surface opposite to the first surface. The welding part includes a hatching area in which a surface roughness of the second surface is larger than that of the second surface in the pattern part.

Abstract: A method for fabricating a semiconductor device includes: forming a gate structure including a source side and a drain side over a substrate, wherein a dielectric material and a columnar crystal grain material are stacked over the substrate; doping a chemical species on the drain side of the gate structure; and exposing the gate structure doped with the chemical species to a re-growth process in order to thicken the dielectric material on the drain side of the gate structure.

Abstract: The present disclosure relates to a semiconductor device structure with fine patterns and a method for preparing the semiconductor device structure for preventing the collapse of the fine patterns. The semiconductor device structure includes a first inner spacer element disposed over a top surface of a semiconductor substrate. The first inner spacer element includes a first portion, a second portion, and a third portion between the first portion and the second portion. A height of the first portion and a height of the second portion are less than a height of the third portion, and a width of the first portion increases continuously as the first portion extends toward the top surface of the semiconductor substrate. The semiconductor device structure also includes a first outer spacer element disposed over the second portion of the first inner spacer element.

Abstract: In order to obtain a light emitting module with a less unevenness of luminance, provided is a method for manufacturing a light emitting module comprising: preparing a light emitter and a light-transmissive light guide plate, the light emitter comprising a light emitting element, the light guide plate having a first main surface serving as a light emitting surface from which light is emitted outside and a second main surface located opposite to the first main surface and having a concave portion, the concave portion comprising a side surface and a bottom surface that is smaller than an opening of the concave portion in a cross-sectional view; fixing the light emitter to the bottom surface of the concave portion via a bonding member; and forming a wiring at an electrode of the light emitting element.

Abstract: The inventive concept relates to a substrate support unit. The substrate support unit includes a chuck stage having an inner space defined by a base surface and sidewalls, a heating unit provided in the inner space, the heating unit including a base plate having a disk shape with an opening in the center and a heat generation part mounted on the base plate and having heating light sources that emit light energy, a quartz window that covers the inner space and has an upper surface on which a substrate is placed, and a reflective member that reflects light energy lost in a lateral direction of the chuck stage toward the substrate.

Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a wiring layer on or above the semiconductor substrate, the wiring layer having a first metal layer and a second metal layer in contact with the first metal layer, a capacitor lower electrode on or above the semiconductor substrate, the capacitor lower electrode being the same material as the second metal layer, a capacitor insulating film on the capacitor lower electrode, and a capacitor upper electrode on the capacitor insulating film. A distance from the semiconductor substrate to an upper face of the capacitor lower electrode is equal to or less than a distance from the semiconductor substrate to an upper face of the wiring layer, and a distance from the semiconductor substrate to a lower face of the capacitor lower electrode is greater than a distance from the semiconductor substrate to a lower face of the wiring layer.

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

Abstract: A semiconductor device includes a stacked transistor memory cell. The stacked transistor memory cell includes a bottom tier including a plurality of bottom transistors including at least one non-floating transistor and at least one floating transistor. The at least one floating transistor has at least one terminal being electrically disconnected from other transistors of the stacked transistor memory cell. The stacked transistor memory cell further includes a top tier including a at least one top transistor, and a cross-coupling including epitaxial region (epi) connections and gate to epi connections between the top tier and the bottom tier.

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

Abstract: An electronic device includes a first substrate having a wiring trace, a second substrate having an external terminal, a first electronic component disposed on a first surface of the first substrate, a second electronic component electrically connected to the first electronic component and disposed on a second surface of the first substrate, a mold layer encapsulating the first electronic component, and a conductive member disposed in the mold layer. The conductive member electrically connects the first substrate to the second substrate. A step is formed at an end of the mold layer, and the conductive member is exposed at the step. A distance between the first substrate and the second substrate is smaller than a distance between the first surface of the first substrate and a surface of the first electronic component that is positioned opposite to the first substrate.

Abstract: An e-fuse and a manufacturing method thereof, and a memory cell are provided. The method includes: providing a semiconductor substrate including a preset active region; forming an isolating region on the substrate, where the isolating region and the preset active region have a height difference and are connected by at least one side wall; forming a negative electrode and a positive electrode on the preset active region; and forming a fuse link on the side wall for connecting the negative electrode and the positive electrode. Accordingly, the line width of the fuse link is out of the limitation of the limit line width of the semiconductor process, the actual line width of the e-fuse may be smaller than the limit line width of the semiconductor process, and low fusing current is required for fusing.

Abstract: Bismaleimides (BMI) exhibit excellent heat resistance (high Tg and high resistance to thermal decomposition) compared to epoxy resins and phenolic resins, and therefore, in recent years, more attention is paid to bismaleimides as a resin material for the next-generation devices represented by SiC power semiconductors, in addition to the investigation on the use of bismaleimides for electronic material applications. As such, conventional BMI's are known as highly heat-resistant resins; however, there is a demand for a resin having higher heat resistance for advanced material applications and the like. Thus, an object of the invention is to provide a novel maleimide compound having superior heat resistance. Disclosed is a substituted or unsubstituted allyl group-containing maleimide compound having a structure with three or more benzene rings, having one or more groups each having a substituted or unsubstituted allyl group, and having one or more maleimide groups.

Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.

Abstract: To provide a magnetic storage element, a magnetic storage device, and an electronic device which store multi-value information with a simpler structure.

Abstract: A method for fabricating a semiconductor device including a vertical transistor includes etching a longitudinal end portion of a fin on a substrate to form a gap exposing the substrate, forming a top source/drain region, and forming, around a horizontal portion and a vertical portion of a bottom source/drain region disposed on the substrate, a contact wrapping in a region including a location where the longitudinal end portion of the fin was removed by the etching.

Abstract: The semiconductor device according to the present technology includes a hollow region or an insulating region. The hollow region or the insulating region is provided under a channel that is formed between a source of a first semiconductor type and a drain of the first semiconductor type in a body region of a second semiconductor type in a transistor, the body region being provided between the source and the drain.

Abstract: A semiconductor device has a substrate comprising a carrier and an interposer disposed on the carrier. An electrical component is disposed over a first surface of the interposer. An interconnect structure is disposed over the first surface of the interposer. An encapsulant is deposited over the electrical component, interconnect structure, and substrate. A trench is formed through the encapsulant and interposer into the carrier. A shielding layer is formed over the encapsulant and into the trench. The carrier is removed after forming the shielding layer.