Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

Abstract: A method of contaminant detection comprises exposing a wafer comprising one or more contaminants to microdroplets of an oxidizer to form an oxide on a surface of the wafer, exposing the oxide to an etchant to remove the oxide and leave the one or more contaminants on the surface of the wafer, and determining a composition of the one or more contaminants. Additional methods and related tools are also disclosed.

Abstract: Various embodiments of energy storage elements for use in power converters are described. In one example embodiment, briefly, an integrated circuit (IC) for use with a power converter may comprise a first layer comprising a first set of devices disposed on a device face thereof; a second layer comprising a second set of devices disposed on a device face thereof; a first interconnect structure to be disposed between the first layer and an electrical interface, the first interconnect structure to electrically couple the first set of devices to one or more thru vias; and a second interconnect structure to be disposed between the first layer and the second layer, the second interconnect structure to electrically couple the second set of devices to the one or more thru vias. Likewise, in some instances, one or more thru vias may extend through at least one of the following: the first layer; the second layer; or any combination thereof.

Abstract: A computer program comprising instructions which, when executed by a computer, cause the computer to carry out a sketching routine in a video game, wherein, in the sketching routine, a character controlled by a user produces a sketch of one or more features in the character's field of view. A computer-readable medium having such a computer program stored thereon is also provided.

Abstract: A ceramics substrate includes: a substrate body; and an electric conductor patient that is provided in the substrate body. The substrate body is made of ceramics containing aluminum oxide. The electric conductor pattern is a sintered body that contains tungsten as a main component and further contains nickel oxide, aluminum oxide and silicon dioxide.

Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.

Abstract: This lid material for packages is a lid material for packages which is bonded to a package substrate, and the lid material for packages includes: a glass member including a bonding portion provided in a planar frame shape and a light transmitting portion provided inside the bonding portion; one or more metallized layers formed in a frame shape at the bonding portion of the glass member; and one or more Au—Sn layers provided on the metallized layers and having a frame shape having a width of 250 ?m or less.

Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.

Abstract: A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: A method of fabricating a semiconductor device and a semiconductor processing apparatus are provided. The method of fabricating a semiconductor device comprises preparing a semiconductor substrate having a front side and a back side, opposing each other, and forming a material layer on the semiconductor substrate. The material layer is formed on at least a portion of the back side of the semiconductor substrate while being formed on the front side of the semiconductor substrate. The material layer formed on the at least a portion of the back side of the semiconductor substrate is removed, while the material layer formed on the front side of the semiconductor substrate remains. A semiconductor process is performed to fabricate the semiconductor device using the material layer remaining on the front side of the semiconductor substrate.

Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

Abstract: A modular LED heater and an LED array are disclosed. The modular LED heater comprises a base having one or more internal conduits through which a coolant fluid may flow. The base also includes a plumbing port on one side wall of the base and a recessed port on an opposite side of the base. These ports are configured such that the plumbing port of one modular LED heater can be inserted into the recessed port of the adjacent modular LED heater to form a fluid-tight seal. A printed circuit board having a plurality of LEDs is disposed on the front surface of the base. Further, in some embodiments, the base includes one or more wedge clamps on its side walls used to lock the modular LED heater to an adjacent modular LED heater. An LED array may be created by assembling a plurality of these modular LED heaters.

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Abstract: A machining apparatus for a curved plate includes a holder that holds a main surface of a curved plate having curved surfaces on both main surfaces; a machining device that machines an outer circumference of the curved plate held by the holder; a movable frame that retains the machining device; a driver that moves the movable frame to move a machining point of the curved plate held by the holder; a controller that controls the driver; and a guide that guides the movable frame along the outer circumference of the curved plate held by the holder.

Abstract: A substrate heating apparatus includes: a substrate support configured to substantially horizontally support a substrate; a heater provided below the substrate support substantially parallel to the substrate, and having a predetermined planar shape; and a side portion extending downward from an outer peripheral portion of the heater.

Abstract: A semiconductor device includes a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.