Abstract: In an embodiment, a device includes: a first and second integrated circuit die; and a hybrid redistribution structure including: a first photonic die; a second photonic die; a first dielectric layer laterally surrounding the first photonic die and the second photonic die, the first integrated circuit die and the second integrated circuit die being disposed adjacent a first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a major surface of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; a second dielectric layer disposed adjacent a second side of the first dielectric layer; and a waveguide disposed between the first dielectric layer and the second dielectric layer, the waveguide optically coupling the first and second photonic dies.

Abstract: An interactive environment image may be projected onto one or more surfaces, and interaction with the projected environment image may be detected within a three-dimensional space over the one or more surfaces. The interactive environment image may be a three dimensional image, or it may be two dimensional. An image is projected onto a surface to provide a visual representation of a virtual space including one or more of the virtual objects, which may be spatially positioned. User interaction with the projected visualized representation of the virtual space may be detected and, in response to user interaction, the projected visualized representation may be changed.

Abstract: A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals onto a substrate, and exposing the substrate to a silicon-containing precursor in a non-plasma environment to form monolayers of a silicon-containing dielectric material on the substrate. Additional methods are also described, as are semiconductor device structures including the silicon-containing dielectric material and methods of forming the semiconductor device structures.

Abstract: A manufacturing method of monocrystalline silicon includes: disposing a flow regulator including a body in a form of an annular plate, provided under a heat shield, surrounding monocrystalline silicon; controlling an internal pressure of a chamber to 20 kPa or more during growth of monocrystalline silicon; keeping the flow regulator spaced from a dopant-added melt; and introducing inert gas into between the monocrystalline silicon and the heat shield to divide the inert gas into a first flow gas and a second flow gas.

Abstract: There are disclosed herein various implementations of a semiconductor device including a group III-V layer situated over a substrate, and a phase-change material (PCM) radio frequency (RF) switch situated over the group III-V layer. The PCM RF switch couples a group III-V transistor situated over the group III-V layer to one of an integrated passive element or another group III-V transistor situated over the group III-V layer. The PCM RF switch includes a heating element transverse to the PCM, the heating element underlying an active segment of the PCM. The PCM RF switch is configured to be electrically conductive when the active segment of the PCM is in a crystalline state, and to be electrically insulative when the active segment of the PCM is in an amorphous state.

Abstract: A method for polishing a silicon wafer, including: a first polishing step of polishing a silicon wafer surface by bringing the wafer held by a polishing head into sliding contact with a polishing pad attached to a turn table while supplying an aqueous alkaline solution containing abrasive grains onto the polishing pad, and a second polishing step of polishing the silicon wafer surface by bringing the wafer into sliding contact with the polishing pad while supplying an aqueous alkaline solution containing a polymer without containing abrasive grains onto the polishing pad, wherein the surface temperature of the polishing pad is controlled such that the surface temperature of the polishing pad in the second polishing step is higher than the surface temperature of the polishing pad in the first polishing step by 2° C. or more. This successfully achieves both of higher flatness and reduction in surface roughness.

Abstract: A substrate processing method includes a substrate rotating step of rotating a substrate in a horizontal posture, a processing liquid supplying step of supplying a processing liquid to an upper surface of the substrate which is being rotated in the substrate rotating step, a liquid film state monitoring step of monitoring a state of a liquid film formed on the upper surface of the substrate by the processing liquid supplied to the upper surface of the substrate, and a substrate rotational speed changing step of changing rotational speed of the substrate in accordance with the state of the liquid film monitored in the liquid film state monitoring step during execution of the processing liquid supplying step.

Abstract: A silver sintering preparation comprising: (A) 30 to 88 wt.-% of silver flake particles having a mean particle diameter (d50) in the range of >1 to 20 ?m, (B) 5 to 30 wt.-% of at least one silver precursor, (C) 1 to 10 wt.-% of an organic polymer system, and (D) 6 to 30 wt.-% of organic solvent, wherein the organic polymer system (C) is chemically essentially stable at temperatures <300° C. and forms a continuous phase together with the organic solvent (D).

Abstract: The present disclosure provides a package structure including a redistribution layer and a die. The redistribution layer includes a switch circuit portion and a redistribution portion, the switch circuit portion includes a transistor, and the redistribution portion is adjacent to the switch circuit portion. The die overlaps the redistribution portion, wherein the transistor is electrically connected to the die.

Abstract: A device for inspecting a bump height includes an illumination device, an imaging device, and a control device. The illumination device irradiates a substrate with light. The substrate includes a resist and a bump formed on an opening portion of the resist. The imaging device images a pattern of the resist and the bump. The control device evaluates a height of the bump based on a luminance value of image data of the pattern obtained by the imaging device.

Abstract: A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.

Abstract: Methods for forming high aspect-ratio conductive regions of a metallization network with reduced grain boundaries are described. Aspects of the invention include forming a trench in a dielectric material on the substrate. A conductive material is formed in the trench, wherein the conductive material includes a first grain boundary level. Portions of the dielectric material are removed to expose sidewalls of the conductive material. The conductive material is annealed to reduce the first grain boundary level.

Abstract: A mask assembly includes a mask frame, a mask on the mask frame and including at least one opening through which a deposition material passes, and a stick on the mask frame and extending over the opening, wherein the stick includes a stick body portion connected to the mask frame and extending over the opening, and a protrusion protruding from the stick body portion toward the opening.

Abstract: A method of manufacturing a semiconductor device includes forming a precursor structure including a substrate having a via hole, a liner on a sidewall of the via hole, a conductor in the via hole, a first and a second insulating layers respectively on the top and bottom surfaces, and a first and a second redistribution layers in contact with the conductor through a first hole in the first insulating layer and a second hole in the second insulating layer. A first opening and a second opening are then respectively formed in the first insulating layer and the second insulating layer to expose a portion of the liner. The liner is then etched through the first opening and the second opening to form an air gap surrounding the conductor. The first opening and the second opening are then filled to seal the air gap.

Abstract: Disclosed is a processing method for performing a processing corresponding to a processing gas in a plurality of processing containers which are connected to a gas supply source, and at least some of which have different lengths of pipes to the gas supply source. The processing method includes simultaneously supplying the processing gas from the gas supply source to the plurality of processing containers, and individually supplying the processing gas from the gas supply source to the plurality of processing containers or to some of the plurality of processing containers.

Abstract: The present disclosure relates to a detector device assisted by majority current, comprising a semiconductor layer of a first conductivity type, at least two control regions of the first conductivity type, at least one detection region of a second conductivity type opposite to the first conductivity type and a source for generating a majority carrier current associated with an electrical field, characterized in that it further comprises isolation means formed in the semiconductor layer and located between said two control regions, for deflecting the first majority carrier current generated by the first source between said two control regions and, hence, increasing the length of the first majority current path, reducing the amplitude of said first majority carrier current and, therefore, reducing the power consumption of the detector device.

Abstract: An IGBT with improved switching characteristics is disclosed. The contact hole CH1 in which the emitter potential electrode EE is buried is formed at a position overlapping with the trench T 1 in which the gate electrode G 1 is buried in plan view. The upper surface of gate electrode G1 in trench T1 is retracted, and an interlayer insulating film IL2 is formed on the top of trench T1. Since the bottom of the contact hole CH1 is located on the interlayer insulating film IL2 in the trench T 1 and in the base region PB, the emitter potential electrode EE is not in contact with the gate electrode G 1.

Abstract: To provide a high-quality group III nitride semiconductor. A group III nitride semiconductor including an n-GaN layer composed of AlxGa1-xN (0?x<1), an InGaN layer disposed on the n-GaN layer and composed of InGaN, an n-AlGaN layer disposed on the InGaN layer and composed of n-type AlyGa1-yN (0?y<1), and a functional layer disposed on the n-AlGaN layer, wherein the concentration of Mg in the n-GaN layer is higher than the concentration of Mg in the n-AlGaN layer.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first columnar body, and a second columnar body. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked along a first direction. The first columnar body extends through the stacked body. The second columnar body extends through the stacked body, and is aligned with the first columnar body along the first direction. The second columnar body includes a second channel film. The first columnar body includes a first channel film, a core surrounded by the first channel film, and a conductive layer. The conductive layer is in contact with the second channel film of the second columnar body and the first channel film of the first columnar body.

Abstract: A display apparatus includes a substrate including a first area, a second area surrounding the first area, and a third area between the first area and the second area. A plurality of display elements disposed in the second area include a first display element and a second display element spaced apart from each other. A thin-film encapsulation layer includes an organic encapsulation layer covering the plurality of display elements. An inorganic encapsulation layer is on the organic encapsulation layer. A planarization layer partially covers the thin-film encapsulation layer in the third area. The inorganic encapsulation layer includes a first surface facing the planarization layer and a second surface facing in an opposite direction. The first surface has a roughness that is greater than a roughness of the second surface. In addition, other various embodiments may be provided.