Abstract: In one embodiment, a virtual tape storage (VTS) system includes random access storage; sequential access storage; support for at least one virtual volume; a storage manager having logic for determining a physical block ID (PBID) that corresponds to a starting logical block ID (SLBID); and logic for copying a portion of a logical volume from the sequential access storage to the random access storage without copying the entire logical volume. Other embodiments are disclosed also.

Abstract: A system includes an associative memory, a first table, a second table, a comparator, and an updater. The associative memory may include data and associations among data and may be built from the first table. The first table may include a record with a first and second field. The associative memory may be configured to ingest the first field and avoid ingesting the second field. The second table may include a record with a third field storing information indicating whether the first field has been ingested by the associative memory or has been forgotten by the associative memory. The comparator may be configured to compare the first and second table to identify one of whether the first field should be forgotten or ingested by the associative memory. The updater may be configured to update the associative memory by performing one of ingesting or forgetting the first field.

Abstract: The disclosure is related to systems and methods of dynamic dataflow in a multiple cache architecture. In an embodiment, a system having a data storage device with a multiple cache architecture may detect at least one attribute affecting a data storage workload or data storage performance. The system may select at least one of a plurality of data flow schemes based on the at least one attribute, which may be done to optimize the data storage workload for various conditions. In another embodiment, a data storage controller may automatically and dynamically select one of multiple data flow schemes within a data storage device having a multiple cache architecture. The data storage controller may monitor attributes to determine which data flow scheme to select for various workloads of the data storage device.

Abstract: A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

Abstract: A virtual data storage system stores data as data objects to a plurality of storage devices in accordance with storage management policies. Storage pools define groups of medial that are to be treated in a uniform manner. A policy is composed of a series of policy copy/delete rules that direct movement of data objects into the storage pools. Copy and delete actions are preformed to manage copies of data objects among the storage pools in accordance with the policy. As an extension of the storage management policies, the process of creating export media sets is automated. These processes can also be used to create backup media. When an export media set is created, subsequent commands are prevented from modifying the media in the export media set. When a backup is created, subsequent commands are prevented from overwriting media containing data referred to by the manifest media for the backup.

Abstract: An object storage system comprises one or more computer processors or threads that can concurrently access a shared memory, the shared memory comprising an array of equally-sized cells. In one embodiment, each cell is of the size used by the processors to represent a pointer, e.g., 64 bits. Using an algorithm performing only one memory write, and using a hardware-provided transactional operation, such as a compare-and-swap instruction, to implement the memory write, concurrent access is safely accommodated in a lock-free manner.

Abstract: The electronic device and a preventing data loss method adapted for an electronic device are disclosed. The electronic device includes a storage unit to store an application. The method includes the steps: running an application in response to user input. Detecting the user input in real time and starting to time when the user input is not detected, and evaluating whether the period timed reaches a predetermined time period. If the predetermined time period is elapsed, suspending the application and detecting an electric energy of a battery providing power to the electronic device; evaluating whether the electric energy of the battery reaches a preset value. If the electric energy of the battery reaches the preset value, making a backup of process data associated with the suspended application in the storage unit.

Abstract: Embodiments of the system described herein can be implemented in a software application that runs on a host device or is embedded in a logic or memory device such as a gate array, EEPROM, a control, or dynamical system. The system embodiment allows a set of similar or dissimilar intelligent devices or sensors, which may be interconnected with any type of network or bus, to replicate data between themselves for the purpose of remote backup, redundancy, content distribution, or measurements. The attributes of the data, which may be changed or created on one device or passed through the device, are tracked and journaled in volatile or non-volatile storage in a first phase. This occurs in real-time as the data changes or passes through the device. In a second phase, the attributes that match patterns pre-specified in a configuration are used to decide what changes or the content to replicate to one or more devices. In a third phase, the data is replicated.

Abstract: Various embodiments of a semiconductor system, a semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.

Abstract: A storage medium management part includes a stored data amount adjustment part that: stores a maximum data amount which the storage medium can store at the time of startup of a storage control device, and a stored data amount which is an initial stored amount, in a data amount storage part; upon receiving a write amount of a data in response to a write request, writes a new stored data amount calculated by adding the write amount to the already stored data amount, over the already stored data amount; calculates a free space by subtracting the stored data amount from the maximum data amount; determines a deletion amount of the data if the free space does not takes a value not less than a prescribed value; and writes a newly-calculated stored data amount calculated by subtracting the deletion amount from the stored data amount, over the stored data amount.

Abstract: A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue.

Abstract: A method is provided for managing errors in a virtualized information handling system that includes an error detection system and a hypervisor allowing multiple virtual machines to run on the information handling system. The hypervisor may assign at least one memory region to each of multiple virtual machines. The error detection system may detect an error, determine a physical memory address associated with the error, and report that address to the hypervisor. Additionally, the hypervisor may determine whether the memory region assigned to each virtual machine includes the physical memory address associated with the error. The hypervisor may shut down each virtual machine for which a memory region assigned to that virtual machine includes the physical memory address associated with the error, and not shut down each virtual machine for which the memory regions assigned to that virtual machine do not include the physical memory address associated with the error.

Abstract: Apparatus, systems, and methods are disclosed for managing concurrent storage requests. A multiple storage request receiver module is configured to recognize at least two storage requests from clients for data in storage devices of a storage device set. The at least two concurrent storage requests address a common portion of data. A sequencer module is configured to determine a first storage request and a second storage request from the concurrent storage requests by way of selection criteria. The sequencer module is configured to ensure completion of the first storage request prior to executing the second storage request by receiving an acknowledgment from each of the storage devices of the storage device set that received portions of the first storage request. The portions may be sent to the storage devices to execute the first storage request.

Abstract: Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.

Abstract: A method, computer program product, and computing system for record sorting is described. The method may comprise splitting an incoming record into a separate key block and payload block. The method may further comprise storing the key block in a first memory. The method may also comprise assigning the payload block an address in a second memory at the beginning of a sort. Moreover, the method may store, with the key block in the first memory, the address of the payload block in the second memory. Additionally, the method may store the payload block at the address in the second memory.

Abstract: This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level.

Abstract: A secure memory interface includes a reader block, a writer block, and a mode selector for detecting fault injection into a memory device when a secure mode is activated. The mode selector activates or deactivates the secure mode using memory access information from a data processing unit. Thus, the data processing unit flexibly specifies the amount and location of the secure data stored into the memory device.

Abstract: A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Abstract: The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.