Abstract: An electronic storage device (320) for connecting with a host system (100) includes a storage unit (360) including at least one memory segment which has at least one physical block, a memory unit (350) receiving access commands sent from the host system, and a control unit (340) connecting with said memory unit. Each of the access commands contains at least a logical address which corresponds to a physical block. The control unit determines the command execution order of the access commands according to adjacent extent of the physical blocks in said memory segment to which the logical addresses of said access commands correspond. A control method of the electronic storage device is also disclosed in the present invention.

Abstract: A method for replicating a deduplicated storage system is disclosed. A stream of data is stored on an originator deduplicating system by storing a plurality of deduplicated segments and information on how to reconstruct the stream of data. The originator deduplicating system is replicated on a replica system by sending a copy of the plurality of deduplicated segments and information on how to reconstruct the stream of data to the replica system. A first portion of the deduplicated segments stored on the originator deduplicating system that is corrupted is identified. A copy of the first portion of the deduplicated segments is requested to be sent by the replica system to the originator deduplicating system.

Abstract: Disclosed are a system and method to preserve and recover unwritten data present in data cache of a disk subsystem across power outages. In one embodiment, a method of a controller is described. The method includes applying a write-back technique between a host server and a data store, accessing a dirty data in a cache memory during a power outage. The method may apply an algorithm for efficiently offloading the dirty data to a non-volatile storage device during the power outage. In addition the method may apply the algorithm to efficiently transfer the dirty data from the non-volatile storage device to the data store when power is restored.

Abstract: According to one embodiment, an information processing apparatus includes a main memory, a first storage, a second storage, a first writing module, and a second writing module. A first storage is configured to store a file for executing an operating system. A first writing module is configured to write writing position information which indicates a writing position of data written in the second storage and is written to a predetermined position to the second storage, to the main memory. The second writing module is configured to write, to the first storage, the writing position information in the main memory to a predetermined write area in the first storage in a case of a crash of the operating system. The third writing module is configured to write the writing position information to the predetermined position in the second storage.

Abstract: An active/active remote mirroring system, for example an active/active SRDF system, provides for remote mirroring between multiple storage volumes, e.g., a first storage device and a second storage device, in which the storage devices may both be active. A plurality of hosts may be coupled to either the first storage device, the second storage device, or both to conduct read and write operations from and to the storage devices, for example to nearest device. The hosts may be part of an application cluster. The first storage device and the second storage device may be connected via a link, such as an SRDF link, for providing remote mirroring capabilities between the storage volumes. In various embodiments the first and second storage devices may be separate devices, volumes, or portions thereof, and/or may be different portions of the same storage device.

Abstract: Embodiments of methods to securely bind a disk cache encryption key to a cache device are generally described herein. Other embodiments may be described and claimed.

Abstract: A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

Abstract: Systems, methods, and computer readable media for improving synchronization performance after partially completed writes are disclosed. According to one aspect, a method for improving synchronization performance after partially completed writes includes receiving, from a requesting entity, data to be written to storage. The data to be written is sent to each of a plurality of data storage entities, including a primary data storage entity and at least one secondary data storage entity for providing a duplicate of the primary data storage entity. For each of the plurality of data storage entities, the portion of the data that was stored to the respective data storage entity is determined.

Abstract: A non-volatile solid-state storage subsystem, such as a non-volatile memory device, maintains usage statistics reflective of the wear state, and thus the remaining useful life, of the subsystem's memory array. A host system reads the usage statistics information, or data derived therefrom, from the subsystem to evaluate the subsystem's remaining life expectancy. The host system may use this information for various purposes, such as to (a) display or report information regarding the remaining life of the subsystem; (b) adjust the frequency with which data is written to the subsystem; and/or (c) select the type(s) of data written to the subsystem.

Abstract: The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data set from the hard disk drive to a spare solid-state disk drive during a solid-state disk drive rebuild process. The data subset includes a first amount of data and the data set includes a second amount of data, where the first amount of data is less than the second amount of data. The method may further include the step of receiving a read request from a host server requesting the data subset. The method further includes the step of directing the read command to the spare solid-state disk drive.

Abstract: A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.

Abstract: Embodiments of the present invention provide a method, system and computer program product for dual timer fragment caching. In an embodiment of the invention, a dual timer fragment caching method can include establishing both a soft timeout and also a hard timeout for each fragment in a fragment cache. The method further can include managing the fragment cache by evicting fragments in the fragment cache subsequent to a lapsing of a corresponding hard timeout. The management of the fragment cache also can include responding to multiple requests by multiple requestors for a stale fragment in the fragment cache with a lapsed corresponding soft timeout by returning the stale fragment from the fragment cache to some of the requestors, by retrieving and returning a new form of the stale fragment to others of the requestors, and by replacing the stale fragment in the fragment cache with the new form of the stale fragment with a reset soft timeout and hard timeout.

Abstract: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Abstract: Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to nested transaction rollback and provide a method, system and computer program product for dynamic nest level determination for nested transaction rollback. In an embodiment of the invention, a nested transaction rollback method can be provided. The method can include detecting a violation of a block of memory accessed within a set of nested transactions, retrieving a tentative rollback level for the violation, discarding a speculative state for the block of memory at each level of the set of nested transactions up to and including the tentative rollback level, refining the tentative rollback level to a lower level in the set of nested transactions, and additionally discarding a speculative state for the block of memory at additional levels in the set of nested transactions up to and including the refined rollback level.

Abstract: Described techniques increase runtime performance of workloads executing on a hypervisor by executing virtualization-aware code in an otherwise non virtualization-aware guest operating system. In one implementation, the virtualization-aware code allows workloads direct access to physical hardware devices, while allowing the system memory allocated to the workloads to be overcommitted. In one implementation, a DMA filter driver is inserted into an I/O driver stack to ensure that the target virtual memory of a DMA transfer is resident before the transfer begins. The DMA filter driver may utilize a cache to track which pages of memory are resident. The cache may also indicate which pages of memory are in use by one or more transfers, enabling the hypervisor to avoid appropriating pages of memory during a transfer.

Abstract: In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Abstract: The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region.

Abstract: In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy. The controller may be configured to utilize the file cache segment in accordance with information related to the block cache segment and to utilize the block cache segment in accordance with information related to the file cache segment.

Abstract: A method is provided for managing errors in a virtualized information handling system that includes an error detection system and a hypervisor allowing multiple virtual machines to run on the information handling system. The hypervisor may assign at least one memory region to each of multiple virtual machines. The error detection system may detect an error, determine a physical memory address associated with the error, and report that address to the hypervisor. Additionally, the hypervisor may determine whether the memory region assigned to each virtual machine includes the physical memory address associated with the error. The hypervisor may shut down each virtual machine for which a memory region assigned to that virtual machine includes the physical memory address associated with the error, and not shut down each virtual machine for which the memory regions assigned to that virtual machine do not include the physical memory address associated with the error.