Patents Examined by John P Fishburn
  • Patent number: 8060709
    Abstract: Computer file archiving systems and techniques are described. Various aspects include wide area high-availability file archiving, volume-level management capabilities of archiving systems, and methods and systems for storing file archiving metadata. The methods and systems described can be used individually or in combination.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 15, 2011
    Assignee: EMC Corporation
    Inventors: Anthony Arous, Chenlan Guo, Jeffrey C. Peterson
  • Patent number: 8041882
    Abstract: For NAND flash devices, two specific bounds for the program time are defined in the data sheets: a typical program time, during which more than 50% of all pages are programmed, and a maximum program time. Reduction of the maximum program time to an effective program time is possible using the following method for writing to a flash memory, comprising the steps of specifying an effective program time that is between typical and maximum program time, writing first data to the flash memory, after the effective program time checking if the programming cycle is finished, if it is finished writing second data to the flash memory, and if it is not finished writing the at least second data to a buffer memory and marking them as not to be overwritten, repeating the previous steps as long as further data are to be stored, determining a free location in a flash memory, and copying the at least second data from the buffer memory to the determined location in the flash memory.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: October 18, 2011
    Assignee: Thomson Licensing
    Inventors: Joern Jachalsky, Marko Luetjen
  • Patent number: 8037254
    Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST1-ST4). A streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N; IM) and the memory (MEM). Said streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4). A buffer managing unit (BMU) is provided for managing a temporarily storing of data streams (ST1-ST4) in the buffer (B) in a first and second operation mode (1OM; 2OM). In the first operation mode (1OM), data from the data streams (ST1-ST4) to be stored in the memory (MEM) are temporarily stored in the buffer (B) until a portion of the buffer (B) is occupied.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: October 11, 2011
    Assignee: NXP B.V.
    Inventors: Artur Burchard, Ewa Hekstra-Nowacka, Atul P. S. Chauhan
  • Patent number: 8037271
    Abstract: Methods copying data from one location to another in a main memory of a cell processor are disclosed. A portion of the data is transferred a first main memory location to the local store of one or more SPU and then transferred from the local store to a second main memory location.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: October 11, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Antoine Labour, Richard B. Stenson, John P. Bates
  • Patent number: 8028138
    Abstract: A method of replicating a deduplicated storage system is disclosed. The method comprises requesting the state of a replica system. The method further comprises sending a container to the replica system and sending a file system log record to the replica system.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: September 27, 2011
    Assignee: EMC Corporation
    Inventors: Allan J. Bricker, Richard Johnsson, Greg Wade
  • Patent number: 8024515
    Abstract: A method and apparatus for deferring media writes for emulation drives are provided. By deferring media writes using non-volatile storage, the performance penalty associated with RMW operations may be minimized. Deferring writes may allow the RMW operations to be done while the disk drive is idle. Further, deferring writes may also allow data blocks to be accumulated over time, allowing a full (4K) disk drive block size to be written with a simple write operation, thus making a RMW unnecessary.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 20, 2011
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Daniel J. Auerbach, Spencer W. Ng
  • Patent number: 8019954
    Abstract: Embodiments of the present invention provide a mechanism for an operating system and applications to cooperate in memory management. Applications register with the operating system for cooperative memory management. The operating system monitors the memory and determines a memory “pressure” related to the amount of demand for the memory. As the memory pressure increases, the operating system provides a memory pressure signal as feedback to the registered applications. The operating system may send this signal to indicate it is about to commence evicting pages from the memory or when it has commenced swapping out application data. In response to the signal, the registered applications may evaluate the memory pressure, determine which data should be freed, if any, and provide this information back to the operating system. The operating system may then free those portions of memory relinquished by the applications. By releasing data the system may thus avoid swapping and increase its performance.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: September 13, 2011
    Assignee: Red Hat, Inc.
    Inventors: Henri Han van Riel, Matthias Clasen
  • Patent number: 8019938
    Abstract: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: September 13, 2011
    Assignee: Fusion-I0, Inc.
    Inventors: David Flynn, John Strasser, Jonathan Thatcher, Michael Zappe
  • Patent number: 8001350
    Abstract: A main memory and a hard disk include predetermined serial numbers. A flash memory registers the main memory and hard disk together with their serial numbers. A BIOS reads the serial numbers from the main memory and hard disk. When a read-out serial number is not registered in the flash memory, the BIOS places the information processing apparatus in an unusable state.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Limited
    Inventor: Kei Hiroyoshi
  • Patent number: 7984257
    Abstract: A system for protecting supervisor mode data from user code having a processor which implements a register window architecture supporting as separate window stacks for supervisor and user modes with a transition window in one of the window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, supervisor mode-only memory storing the supervisor mode window stack, and user mode accessible memory storing the supervisor and user mode window stacks.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 19, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventors: David William Funk, Barry Gauke
  • Patent number: 7953930
    Abstract: A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: May 31, 2011
    Assignee: SanDisk Corporation
    Inventor: Steven S. Cheng
  • Patent number: 7945741
    Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for performing a transaction including a transaction head and a transaction tail, the method includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiaowei Shen, Karin Strauss
  • Patent number: 7934055
    Abstract: An apparatus, system, and method are disclosed for a shared, front-end, distributed redundant array of independent drives (“RAID”). A multiple storage request receiver module receives at least two storage requests from at least two clients to store file or object data in one or more storage devices of a storage device set. The storage requests are concurrent and have at least a portion of the data in common. The storage device set includes autonomous storage devices forming a RAID group. Each storage device is capable of independently receiving storage requests from a client over a network. A striping module calculates a stripe pattern and writes N data segments per stripe to N storage devices. A parity-mirror module writes a set of N data segments to parity-mirror storage devices. A sequencer module ensures completion of a first storage request prior to executing a second storage request.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: April 26, 2011
    Assignee: Fusion-Io, Inc
    Inventors: David Flynn, Jonathan Thatcher, Michael Zappe
  • Patent number: 7934050
    Abstract: A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: April 26, 2011
    Assignee: DENSO CORPORATION
    Inventors: Masahiro Kamiya, Kyouichi Suzuki, Naoki Itoh, Hideaki Ishihara
  • Patent number: 7934051
    Abstract: The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibitio
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: April 26, 2011
    Assignee: Spansion LLC
    Inventors: Kenji Shibata, Masahiko Okura, Mitsuhiro Nagao
  • Patent number: 7930498
    Abstract: An apparatus, system, and method for replicating a snapshot volume in a first storage system to a second storage system includes mapping information corresponding to data in the first storage system that is transferred from the first storage system to the second storage system so that a file system in the second storage system can mount the data after replication. Replication of the snapshot volume can be accomplished using a remote copy mechanism. The snapshot volume can be obtained from a primary source volume P-VOL and a differential source volume D-VOL. If the corresponding destination volumes are not known, a search is conducted to locate appropriate volumes in the second storage system. Mapping information regarding these destination volumes is utilized to enable the file system in the second storage system to mount the replicated snapshot volume.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: April 19, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Hidehisa Shitomi
  • Patent number: 7882321
    Abstract: A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Rama K. Govindaraju, Peter H. Hochschild, Bruce G. Mealey, Satya P. Sharma, Balaram Sinharoy
  • Patent number: 7870354
    Abstract: Embodiments of the system described herein can be implemented in a software application that runs on a host device or is embedded in a logic or memory device such as a gate array, EEPROM, a control, or dynamical system. The system embodiment allows a set of similar or dissimilar intelligent devices or sensors, which may be interconnected with any type of network or bus, to replicate data between themselves for the purpose of remote backup, redundancy, content distribution, or measurements. The attributes of the data, which may be changed or created on one device or passed through the device, are tracked and journaled in volatile or non-volatile storage in a first phase. This occurs in real-time as the data changes or passes through the device. In a second phase, the attributes that match patterns pre-specified in a configuration are used to decide what changes or the content to replicate to one or more devices. In a third phase, the data is replicated.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: January 11, 2011
    Assignee: Bakbone Software, Inc.
    Inventor: Justin G. Banks
  • Patent number: 7856523
    Abstract: A Random Access Memory (RAM) based Content Addressable Memory (CAM) architecture is disclosed. In an implementation, the CAM architecture includes a CAM data structure associated with a RAM to store one or more tags and associated data values. Each of the tags includes one or more bit fields which are utilized as an index for referencing a look-up table. One or more look-up tables may be realized for supporting memory operations facilitating efficient transfer modes available in the RAM.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: December 21, 2010
    Assignee: Microsoft Corporation
    Inventor: Ray A. Bittner, Jr.
  • Patent number: 7856526
    Abstract: Access to the physical disks is differentiated as access from a host computer, and access based on processing (data migration processing, copy processing) for storage management. Whether to switch the state of the physical disks from a normal power consumption mode to a power saving mode is determined according to the access from the host computer after the access based on processing for storage management is complete, and the state of the physical disks are switched from the normal power consumption mode to the power saving mode based on the determination result.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: December 21, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Tsukasa Shibayama, Yuri Hiraiwa, Daisuke Shinohara, Nobuyuki Osaki