Abstract: A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.

Abstract: A method of replicating a deduplicated storage system is disclosed. The method comprises storing a stream of data on an originator deduplicating system by storing deduplicated segments and information on how to reconstruct the stream of data. The method further comprises replicating the originator deduplicating system by receiving a copy of the deduplicated segments, information regarding containers for the deduplicated segments, and information on how to reconstruct the stream of data transferred from the originator deduplicating system to the replica system.

Abstract: A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue.

Abstract: A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.

Abstract: A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.

Abstract: Described techniques increase runtime performance of workloads executing on a hypervisor by executing virtualization-aware code in an otherwise non virtualization-aware guest operating system. In one implementation, the virtualization-aware code allows workloads direct access to physical hardware devices, while allowing the system memory allocated to the workloads to be overcommitted. In one implementation, a DMA filter driver is inserted into an I/O driver stack to ensure that the target guest physical memory of a DMA transfer is resident before the transfer begins. The DMA filter driver may utilize a cache to track which pages of memory are resident. The cache may also indicate which pages of memory are in use by one or more transfers, enabling the hypervisor to avoid appropriating pages of memory during a transfer.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.

Abstract: A data formatting system and method to improve data efficiency and integrity in a hard disk are disclosed. One embodiment provides a disk drive system having a plurality of lookup tables which store a plurality of randomizer seeds which may be dynamically encoded into the preamble field of a customer data block if the customer data is deemed marginal. Encoding the randomizer seed into the preamble field prevents adjacent data track mis-writes and mis-reads.

Abstract: A non-volatile solid-state storage subsystem, such as a non-volatile memory device, maintains usage statistics reflective of the wear state, and thus the remaining useful life, of the subsystem's memory array. A host system reads the usage statistics information, or data derived therefrom, from the subsystem to evaluate the subsystem's remaining life expectancy. The host system may use this information for various purposes, such as to (a) display or report information regarding the remaining life of the subsystem; (b) adjust the frequency with which data is written to the subsystem; and/or (c) select the type(s) of data written to the subsystem.

Abstract: Embodiments of the present invention provide a mechanism for an operating system and applications to cooperate in memory management. Applications register with the operating system for cooperative memory management. The operating system monitors the memory and determines a memory “pressure” related to the amount of demand for the memory. As the memory pressure increases, the operating system provides a memory pressure signal as feedback to the registered applications. The operating system may send this signal to indicate it is about to commence evicting pages from the memory or when it has commenced swapping out application data. In response to the signal, the registered applications may evaluate the memory pressure, determine which data should be freed, if any, and provide this information back to the operating system. The operating system may then free those portions of memory relinquished by the applications. By releasing data the system may thus avoid swapping and increase its performance.

Abstract: An information storage device includes one or more semiconductor memories storing management data accompanying content data and being configured to erase data in units of one block, and a controller setting up, in the one or more semiconductor memories, a working area to temporarily store the management data and a storage area to retain all or part of the management data stored in the working area, writing the management data to the working area while monitoring the free space of the working area, moving the management data stored in the working area to the storage area when the free space of the working area falls below a prescribed value, and erasing the management data stored in the working area after the movement of the management data to the storage area.

Abstract: Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.

Abstract: The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data set from the hard disk drive to a spare solid-state disk drive during a solid-state disk drive rebuild process. The data subset includes a first amount of data and the data set includes a second amount of data, where the first amount of data is less than the second amount of data. The method may further include the step of receiving a read request from a host server requesting the data subset. The method further includes the step of directing the read command to the spare solid-state disk drive. The method may further include the step of, prior to completion of copying of the data set from the hard disk drive to the spare solid-state disk drive, reading the data subset from the spare solid-state disk drive based upon the read command.

Abstract: Bulk data transfers by directly accessing a persistent and secured area on the data storage device, e.g., a disk drive having a magnetic storage medium, without relying on the system operating system to execute its read/write operations. For a disk drive, the Protected Area Run Time Interface Extension (PARTIES) technology is applied to create and organize a secured sub-area within a secured storage area. The secured sub-area is a data buffer to and from which large data file transfers can be made with data authenticity and confidentiality. Since this new secured sub-area is not organized and protected by the operating system, it is inherently protected from attack by viruses or Trojan horse software whose effectiveness depends on their ability to maliciously direct the operating system. In addition, the read/write operations bypass command payload limits while reducing data and command validation costs.

Abstract: A buffer management method is provided. A host issues a read command requesting access for a read data block and a write command requesting recording of a write data block. A write buffer is dedicated to store the write data block. A read buffer is dedicated to store the read data block. The method comprises entering the optical disc recorder into a write loop. During the write loop, the optical disc recorder triggering a write command handling procedure in response to the write command; triggering a read command handling procedure in response to the read command; and triggering a pre-recording procedure to prepare the write data block in the write buffer for recording. Wherein contents between the write buffer and read buffer are exchangeable during the write handling procedure, the read handling procedure or the pre-recording procedure.

Abstract: A method of extending the life of a segmented memory device, consistent with certain embodiments involves providing a segmented memory device having a plurality of user defined segments with each segment having a starting and an ending address, and wherein the size and number of the segments is user defined; determining that a threshold number of write operations has been reached by reference to a write counter; copying data from a specified one of the segments to a temporary storage location; shifting the starting and ending address of each segment by a specified address increment; moving data stored in each segment except the specified segment by the specified address increment such that all data in the memory device has been shifted by the specified increment except for the data in the specified one of the segments, wherein data at a last segment is fragmented to wrap from an end of the memory device's addressable locations to a beginning of the memory device's addressable locations; copying the data from

Abstract: A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory.

Abstract: A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Abstract: A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., synchronous dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. The write buffer contents may be preserved across reset or power loss events. The mass storage unit may be a data transport layer, e.g., Ethernet, USB, Bluetooth, etc.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).