Abstract: A storage device batch and parallel processing method adapted for an electronic apparatus, including: (a) connecting a plurality of storage devices to the electronic apparatus; (b) logging device identifiers and disk identifiers of the connected storage devices respectively into a device identifier table and a disk identifier table; (c) obtaining the device identifiers of a predetermined number of the storage devices from the device identifier table and generating a disk table to store the device identifiers of the predetermined number of storage devices; (d) obtaining disk identifiers of the predetermined number of storage devices and recording the disk identifiers to the disk table according to a logging time of each storage device of the predetermined number of storage devices; (e) controlling the storage devices recorded in the disk table performing a data transfer and recursively repeating (c) to (e) until detecting connections between all the storage devices and the electronic apparatus are cutoff.

Abstract: A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: A computer-implemented method is disclosed. The method includes collecting cache-efficiency-indicator values of an at least one cache fragment during operation of a database system over a period of time. Providing approximation-function-parameter values for the collected, cache-efficiency-indicator values, an approximation function representing a relation between a cache-efficiency-indicator and the size of a respective cache fragment. The method continues by providing a set of workload windows based on the approximation-function-parameter values. Next, providing a workload-window information for the set of workload windows, the workload-window information including at least one approximation-function-parameter value representing each determined workload window. The method further includes storing the workload-window information for a comparison based on current, cache-efficiency-indicator values and the workload-window information.

Abstract: A memory system that disperses memory addresses of strings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store strings of data. The CPU is configured to direct the storing and retrieving of the strings of data from the memory at select memory addresses. The address randomizer is coupled between the CPU and the memory. Moreover, the address randomizer is configured to disburse the strings of data throughout locations of the memory by changing the select memory addresses directed by the CPU.

Abstract: Apparatus and methods for storing user data for use in real-time communications (e.g., IM or VoIP) are provided. The apparatus comprises at least a first cache device (e.g., a cache server) and a second cache device for storing user data, wherein the user data stored with the first cache device is mirrored with the second cache device. The apparatus further comprising a server having logic for causing access to the user data (e.g., to respond to or process messages) from the first cache device, if accessible, and from the second cache device if the user data is not accessible form the first cache device. The apparatus may further include logic for causing user data to be restored to the first cache device from the second cache device if the first cache device loses user data (e.g., if the first cache device goes down).

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: A system for transferring data from a disk drive to an external source. The disk drive includes a circuit with embedded firmware that associates internal and output definitions with the data. The definitions and data are provided to the external source which parses the definitions and the data. The parsing engine can output the data in pre-defined format. The embedded firmware associates the same definitions for all data. Thus an external programmer does not have to know, or monitor, the file format and output format of the disk drive to write an external software application.

Abstract: Embodiments include methods, apparatus, and systems for prefetching data in distributed storage systems. One method of software execution includes using input/output (I/O) requests from multiple separate networked storage nodes in a distributed storage system to prefetch data for one of the multiple separate networked storage nodes.

Abstract: An N-port memory architecture is disclosed that stores multi-dimensional arrays so that: (1) N contiguous elements in a row can be accessed without blocking, (2) N contiguous elements in a column can be accessed without blocking, (3) some N-element two-dimensional sub-arrays can be accessed without blocking, and (4) all N/2-element two-dimensional sub-arrays can be accessed without blocking. Second, the architecture has been modified so that the above can happen and that any element can be accessed on any data port. The architecture is particularly advantageous for loading and unloading data into the vector registers of a single-instruction, multiple-data processor, such as that used for video decoding.

Abstract: A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.

Abstract: A method and apparatus are provided for detecting data races that overcome the limitations of the prior art. In some embodiments, this is accomplished by detecting a first access to an object, determining whether the first access is associated with a suspicious pattern, automatically refining a pattern detection granularity from the object to a memory location within the object if a determination is made that the first access is associated with the suspicious pattern, and reporting the data race if a second access associated with the suspicious pattern occurs at the memory location after the pattern detection granularity is refined.

Abstract: A method and apparatus is described herein for supporting heterogeneous local memories. A resource affinity table includes an entry for each local memory mapped into an address space. Each entry associating the corresponding local memory with a logical distance, such as a domain number. During runtime thread scheduling, memory operations, and other tasks are potentially assigned to the local memory devices based on the logical distance associated with each memory in the resource affinity table. As a consequence, heterogeneous memory types or homogeneous memories with different access times may be efficiently combined in a system to achieve large amount of memory at a smaller cost without sacrificing performance by allowing an operating system to make intelligent scheduling choices based on logical distances/access times of the aforementioned memories.

Abstract: A system for protecting supervisor mode data from user code in a register window architecture of a processor is provided. The system, when transitioning from supervisor mode to user mode, setting at least one invalid window bit in the invalid window mask of the architecture additional to the invalid window bit set for the reserved window of the invalid window mask. The additional bit is set for a transition window between supervisor and user data windows.

Abstract: At least a method and system of automatically expanding storage capacity in a data storage device are presented. In one method, the data storage device receives additional hard disk drives. Next, the data storage device receives an expansion option from a user by way of a user interface. The data storage device allocates one or more portions of one or more hard disk drives within the storage device, for use by one or more data pools, based on the expansion option. In one system for automatically expanding storage capacity in a data storage device, the system comprises a memory, one or more processors, and one or more software. One or more data pools are generated using one or more hard disk drives added to the data storage device.

Abstract: A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.

Abstract: A control unit of a hierarchical control apparatus holds information in which one of duplexed library apparatuses is set as a master and the other is set as a slave for each medium in each of the duplexed library apparatuses, and statistical information about each of the library apparatuses. The control unit includes an automatic redundant copy unit detecting that a statistical information of a medium reaches a predetermined amount, replacing the medium with a free medium, and copying data to the free medium, a master/slave setting unit setting the medium to which the data is copied and the other medium as a master or a slave such that a load is even between the duplexed library apparatuses according to the statistical information, and a unit copying and reading the requested data to the disk array apparatus by prioritizing one of the duplexed library apparatuses including the medium set as a master when there is no requested data in the disk array apparatus.

Abstract: A method for accessing shared memory cards from each of plural processor cards is disclosed. The shared memory cards are composed of a shared memory card of an operating system and a shared memory card of a standby system in a redundant configuration, and each of plural processor cards individually access the shared memory cards. Each of the plural processor cards is connected to the shared memory card of the operating system and the shared memory card of the standby system in a point-to-point structure via corresponding serial buses and executes data transmission on a one to one basis to/from the shared memory card of the operating system and the shared memory card of the standby system.

Abstract: A method may include providing a management application with firmware information of a RAID controller and/or system information of a particular set of physical disks forming a particular underlying RAID implementation that is relevant to creating a configuration on the RAID controller of the particular underlying RAID implementation to enable the management application to configure the RAID controller of set of physical disks forming any RAID implementation without prior knowledge of firmware information of the RAID controller and system information of at least one of set of physical disks forming a RAID implementation and determining the configuration of the particular underlying RAID implementation using a decision making process of the management application based on of a firmware information of the RAID controller and system information of the particular set of physical disks forming the particular underlying RAID implementation to determine the configuration of the particular underlying RAID implementat

Abstract: Physical (or prior virtual) machine volumes can be converted to virtual machines at a virtual machine host while the physical machines are running. In one implementation, a volume shadow copy service can be used to create an application (and/or file system)-consistent snapshot of one or more physical machine volumes while the one or more volumes are running. The snapshot data can then be transferred to a mounted virtual hard disk file (dynamic or fixed) at a virtual machine host. Operational information (e.g., boot record, system registry, drivers, devices, configuration preferences, etc.) associated with the virtual hard disk file and the operating system(s) within the virtual machine can then be modified as appropriate to ensure that the corresponding virtual machine is bootable and functional at the virtual machine host. The virtual hard disk file can then be un-mounted, and used as a new virtual machine.