Abstract: A non-volatile solid-state storage subsystem, such as a non-volatile memory device, maintains usage statistics reflective of the wear state, and thus the remaining useful life, of the subsystem's memory array. A host system reads the usage statistics information, or data derived therefrom, from the subsystem to evaluate the subsystem's remaining life expectancy. The host system may use this information for various purposes, such as to (a) display or report information regarding the remaining life of the subsystem; (b) adjust the frequency with which data is written to the subsystem; and/or (c) select the type(s) of data written to the subsystem.

Abstract: According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.

Abstract: A data-processing system and method are disclosed, which include a cached processor for processing data, and a plurality of memory components that communicate with the cached processor. The cached processor is separated from the memory components such that the cached processor provides support for the memory components, thereby providing a diffused memory architecture with diffused memory capabilities. The memory components can constitute, for example, memory devices such as diffused memory, matrix memory, R-Cell memory components, and the like, depending on design considerations.

Abstract: A processor with cache way prediction and method thereof. The processor includes a cache way prediction unit for predicting at least one cache way for selection from a plurality of cache ways. The processor may further include an instruction cache for accessing the selected at least one cache way, where the selected at least one cache way is less than all of the plurality of cache ways. The method includes predicting less than all of a plurality of cache ways for selection and accessing the selected less than all of the plurality of cache ways. In both the process and method thereof, by accessing less than all of the plurality of cache ways, a power consumption and delay may be reduced.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract: An apparatus, system, and method are disclosed for presenting a storage volume as a virtual volume. An attribute module determines a primary volume physical attribute of a primary volume. A presentation module presents the primary volume physical attribute to a host as a target volume virtual attribute of a target volume. A translation module translates communications between a host and the target volume. In one embodiment, a copy module creates a point-in-time copy of the primary volume on the target volume.

Abstract: Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.

Abstract: A system and computer system for improving data integrity and memory performance using non-volatile media. A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., synchronous dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. In one embodiment, the write buffer contents are preserved across reset or power loss events. In one embodiment, the mass storage unit may be a data transport layer, e.g.

Abstract: A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

Abstract: A system and method are provided to manage storage space. The method comprises suspending a request responsive to detecting of a condition indicating a lack of a resource necessary to serve the request; applying a resource management procedure to increase availability of the resource; and, responsive to successful completion of the resource management procedure, serving the request.

Abstract: One embodiment in accordance with the invention is a method for enabling efficient data storage. The method can include determining a maximum value for an element of a data structure, wherein the element can be stored. Also, a minimal bit number is determined that can represent the maximum value. A minimum amount of memory is determined for storing the minimal bit number. The minimum amount of memory is allocated. A determination is made as to where to store the element within the minimum amount of allocated memory.

Abstract: A method of replicating a deduplicated storage system is disclosed. The method comprises requesting the state of a replica system. The method further comprises sending a container to the replica system and sending a file system log record to the replica system.

Abstract: A control system comprises an interface configured to receive a content request from a request source wherein the content request identifies content stored on a storage medium. The control system also comprises a processing system coupled to the interface and configured to process the content request to determine when the request source is a valid destination for the content based on a first identifier stored with the content. The interface is further configured to transfer the content to the request source when the request source is a valid destination.

Abstract: Provided is a storage controller capable of changing a system configuration with scalability. A storage controller blade of the storage controller includes: interface units that each connect to one of a host computer and a disk device; a processor unit that controls a configuration of the storage controller and data access; a memory unit that stores a data cache and configuration information on the interface unit and the processor unit; and a mutual connection unit that connects the interface units, the processor unit, and the memory unit to one another. The processor unit recognizes a form of connection to another storage controller blade over the mutual network, and the connection path to another storage controller blade is set in the mutual connection unit based on the recognized form of connection.

Abstract: Encoding of logical addresses LA upon an off-chip memory bus 22 is performed to produce encoded addresses EA. The portion of the logical address encoded LA [9:3] does not include the least significant bits LA [2:0]. The number of bits LA [2:0] which are unencoded is chosen to correspond to a burst length BL supported by the memory 6 being accessed. Thus, burst mode accesses can be serviced by the memory 6 incrementing its memory address in the normal way. The encoding performed, such as Gray Encoding, reduces the Hamming distance between adjacent memory addresses in a sequence of memory addresses so as to reduce energy consumption.

Abstract: In order to provide a disk array access dynamic control device and a method for improving the performance of a disk array device, the disk array access dynamic control device 1 comprises a composition information storage unit 3 for storing composition information, such as the combination information of disk devices constituting a RAID and the like, a responsible DA control unit 4 for assigning DAs according this composition information or the like and an access unit 6 for reading/writing data from/into a disk device group 2 according to the instruction of an information processing device 5.

Abstract: Embodiments of the present invention provide a mechanism for an operating system and applications to cooperate in memory management. Applications register with the operating system for cooperative memory management. The operating system monitors the memory and determines a memory “pressure” related to the amount of demand for the memory. As the memory pressure increases, the operating system provides a memory pressure signal as feedback to the registered applications. The operating system may send this signal to indicate it is about to commence evicting pages from the memory or when it has commenced swapping out application data. In response to the signal, the registered applications may evaluate the memory pressure, determine which data should be freed, if any, and provide this information back to the operating system. The operating system may then free those portions of memory relinquished by the applications. By releasing data the system may thus avoid swapping and increase its performance.

Abstract: A method for copying a logical volume in a data storage system includes forming a first logical volume, storing in physical storage of the data storage system a quantity of data of the first logical volume, and receiving a first command to copy the first logical volume to a second logical volume. In response to the first command, meta-data is formed having a size that is independent of the quantity of the data. In response to a second command to access the data, the meta-data is used to access the data.

Abstract: A method and system for generating and configuring a data storage object, such as a volume, are described. According to one aspect of the invention, utilizing a graphical user interface, an administrator selects or otherwise identifies an existing data storage object on a data storage system. Next, one or more configuration parameter values associated with one or more configuration parameters of the existing data storage object are extracted from the existing data storage object on the storage system. Finally, a new data storage object is automatically generated and configured according the configuration parameter values extracted from the existing data storage object.