Abstract: Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element.

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements.

Abstract: Methods and apparatus for implementing a high speed serial communications bus with no data loss include a point-to-point bus and a multi-user bus. Both buses are easily implemented in the system software of virtually any microprocessor and make use of virtually any one, two, or three I/O pins of the processor. The point-to-point bus allows two processors (bus users) to communicate via one, two, or three lines coupled to any two I/O pins of each processor. The multi-user bus allows an unlimited number of processors to communicate via three lines coupled to any three I/O pins of each processor. The methods of the invention include providing each processor with communications software by which data is transmitted and received one bit at a time by asserting one or more of the lines of the bus according to a fixed protocol. In the point-to-point bus, when transmitting a ZERO, the first line is a data line and the second line is an acknowledge line.

Abstract: This invention relates to a system for providing programmable configuration protection of a programmable Input/Output device. By configuration protection, it is meant that the programming options of an I/O controller can be set in accordance to a given environment, and then by use of a programming controlled signal, prevent the changing of the programmed environment or remove those programmed options considered unsafe in the now secured environment.

Abstract: A deadlock avoidance system for avoiding interconnection deadlocks between a plurality of data transfer devices includes a controller, a switch interconnector coupled to all of said data transfer devices for interconnecting on a one-to-one basis selected ones of the data transfer device as requesting units to selected ones of said data transfer devices as receiving units. A transfer queue is employed that includes a master transfer register and a slave transfer register, a master register, a slave register and a target register.

Abstract: A data transmission system connects a first device and a second devices, and transmits a signal therebetween. The data transmission system includes a first interface for interfacing the first device and the second device, and a second interface for interfacing the first device and the second device. The first device outputs the signal, with the signal having one of a plurality of voltage ranges. A selector selects one of the first interface and the second interface. The data transmission system also includes an indicator for indicating whether the voltage range of the signal output from the first device is out of a predetermined voltage range of the selected one interface, when the selector selects the one interface.

Abstract: A method of automatically assigning device addresses to devices communicating over a common data bus. Each of the devices may, for example, control an electrically operable system such as a panel assembly that can be disposed over a window opening to control the transmission of light, heat or air through the window and/or for producing different decorative scenes within a room. The method includes sending out a first, trial device address and waiting for an acknowledgement from all of the other devices connected to the data bus to determine whether another device acknowledges that first trial device address as its own. If an acknowledgement is received from any other device, a subsequent, different, trial address is transmitted over the data bus and further waiting ensues to check whether the second trial address has been previously assigned. This process is repeated until the device finds a previously unassigned device address which it then assigns to itself.

Abstract: A system, which is intended for wake-up, restores and wakes up information necessary for resuming a task from a detachable external storage device regardless of whether or not the system has executed hibernation. Historical information showing that hibernation is executed in a system providing in the past external storage device is installed in a predetermined area of an external storage device. The wake-up system checks the history information for executing wake-up. Furthermore, the external storage device stores control information including system configuration information when the task is suspended. The wake-up system compares stored system configuration information with the configuration information of itself. When the configuration information does not agree, restore of information to the main memory to the external storage device is rejected.

Abstract: A power management unit is provided that monitors various portions of a computer system and causes a reduction in the frequencies of the CPU clock signal and the system clock signal during a power conserving state. The power management unit includes a programmable counter for allowing the system designer to vary the length of a wake-up period that occurs in response to an assertion of a timer tick interrupt. An in-service register of an interrupt controller is coupled to the power management unit which thereby allows the power management unit to receive real-time information regarding whether a timer tick interrupt is currently being serviced by the microprocessor. When a timer tick status bit of the in-service register is set, the power management unit causes the CPU clock signal and the system clock signal to be driven at maximum frequencies. When the timer tick status bit clears, the programmable counter begins counting.

Abstract: A drive control system for a microprocessor comprises a switching circuit 5 for varying a drive condition of the microprocessor by varying a processing speed and a power consumption in mutually related manner, an operational state dependent control portion including a status judgment circuit 7, an address monitoring circuit 8, and an address detecting circuit 9, for monitoring the operational state of the microprocessor and controlling the switching circuit 5 for adapting the processing speed to the operational state, and a temperature dependent control portion comprising a temperature sensor 10 and a comparator 11, for lowering the power consumption of the microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected.

Abstract: An improved computer architecture and instruction set that reduces the delays produced by branch instructions. The invention utilizes a branch processor having a branch memory for storing information specifying a plurality of branch instructions that are contained in a code sequence. The branch memory stores information specifying the target address of each branch instruction and the location of the branch instruction with respect to the beginning of the code sequence. The branch processor receives the results of the various comparisons that determine if the conditions associated with the various branches stored in the branch memory are satisfied. The branch processor preferably stores the identity of the branch that is closed to the beginning of the code sequence for which the condition associated therewith has been satisfied. This branch will be referred to as the highest branch enabled.

Abstract: A peripheral device capable of replacing resident microcode with new microcode by download by an application program is disclosed. The disclosed peripheral device comprises a non-volatile memory containing the resident microcode. Further circuitry is responsive to the application program for receiving peripheral device commands. A resident processor, which is coupled to the non-volatile memory and the receiving circuitry, is responsive to the resident microcode, and includes a detector for a received initiator peripheral device command. The resident processor also includes a detector for a transfer disk drive command, which includes the new microcode, and which is received while the disk drive is in a waiting state.

Abstract: A data recognition apparatus of the invention preferably has a data communication apparatus and a portable data reader adapted to communicate therewith. The portable data reader is particularly adapted to substantially extend the time period required before replacing or recharging a portable power source connected thereto. The portable data reader preferably includes a data sensor, a central processor, a display, a user interface, a transceiver, a timer, a portable power source, and a power manager. The power manager is connected in electrical communication with the portable power source, the data sensor, the central processor, the display, the user interface, and the transceiver and the central processor is connected in electrical communication with the timer.

Abstract: A method and system for using a single lock data structure for executing either development or non-development lock primitives contained within a kernel. The kernel includes a mode indication flag, which can be set by the user, for indicating whether the kernel is to operate in a development or a non-development mode. During the execution of the kernel, the mode indication flag is examined and the appropriate set of lock primitives is overlayed. During execution of the kernel in development mode, the single lock data structure is received in the kernel, and a development lock data structure is allocated. The data from the single lock data structure is copied to the development lock data structure, and the lock data structure is overloaded (redefined) as a pointer to the physical address of the development lock data structure. Finally, the lock data structure is initialized to point to the physical address of the development lock data structure.

Abstract: A host adapter for transferring data between a system bus and an input/output (I/O) bus is implemented as an integrated circuit having a data transfer circuit and a status indicator circuit. The status indicator circuit selectively supplies one of a number of status signals from the data transfer circuit as a signal on a status indicator terminal of the host adapter. Therefore, a light emitting diode connected to the status indicator terminal indicates in real time the status of data transfer, such as usage of the system bus, or I/O bus, or execution time of one or more instructions by the host adapter.

Abstract: In the computer 1, the control information for screen display incorporated in the keyboard and software is processed by CPU2 and sent to the display device 6 via the communication controller 5. The microcomputer 7 in the display device 6 fetches the control information from the communication controller 8 and controls a predetermined part of the video circuit 11 or deflection circuit 10. In this case, identification information is sent to the display device 6 from the computer 1 first and when it matches with the identification information stored in the memory 9, the above control is permitted.

Abstract: Remote power source control for a system having a plurality of information processing apparatuses interconnected by a network or networks capable of controlling remote power sources irrespective of different types of networks and providing security checks. Each information processing apparatus is provided with a remote power source controller which is always operated by an auxiliary power source. In instructing a power control of a remote information processing apparatus, control data is transferred between the remote information processing apparatus and a local information processing apparatus. The remote information processing apparatus checks a user ID and a password transmitted from the local processing apparatus prior to controlling its main power source.

Abstract: A microprocessor unit having an interrupt mechanism capable of altering the branching destination depending on the kind of the command being executed upon receipt of an interrupt, thereby offering high degrees of operational freedom and flexibility with a minimum of increase in the scope of MPU circuitry.

Abstract: Data destruction resulting from the conversion of a floppy disk can be prevented during a low-power consumption mode in which the FDD is powered off. The present invention is also designed to prevent data destruction resulting from the conversion of a floppy disk during a low-power consumption mode in which an FDC and an FDD are stopped. In the process of returning to a normal operation mode, an I/O address showing a change line status register of the FDC is set to a stored register of the trap logic (status 173). When the process returns to the normal operation mode and an access to the first status register is trapped, a change line status flag value is rewritten (status 174). The faked OS/driver invalidates the floppy disk allocation information in the main memory.

Abstract: The present invention provides an adapter for utilizing a PCMCIA card in a desktop computer which has at least one card slot and one bay. The adapter includes a logic card configured to be inserted into the card slot of the computer. The logic card has logic thereon to convert PCMCIA bus architecture of the PCMCIA card to the bus architecture of the desktop computer in a bidirectional manner. There may be at least one PCMCIA card receiving slot on the logic card connected to the logic. A first set of external connectors on the logic card is connected to one end of a multi-conductor flexible cable. An outrigger card which includes at least one PCMCIA card is provided which is configured to be inserted into an externally accessible bay of the computer. A second set of connectors on the outrigger card is connected to the opposite end of the multi-conductor flexible cable. Conductors on the outrigger card connect the second set of connectors on the outrigger card to the PCMCIA card receiving slot(s) thereon.