Abstract: An improved small computer systems interface multiplexer (SCSI Mux II) provides for coupling of a computer on a local bus with shared peripheral devices on a global bus. The SCSI Mux II is accessed by a pseudo-operation code that includes two local bus identifiers as the identifier for the SCSI Mux II. Once the SCSI Mux II is identified, the computer accesses the SCSI Mux II as a local bus peripheral device and the SCSI Mux II couples the local bus to the global bus by translating the target peripheral device identification into a global identifier to complete the transfer between the computer and the designated shared peripheral device.

Abstract: An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels.

Abstract: A serial data interface includes a receive data terminal, a received serial data out terminal and an operating power supply terminal. A zero-power receive detector for the serial data interface includes a source for furnishing operating power to the interface. The supply of power from the source is controlled through a microcontroller for switching power to the interface. The microcontroller is coupled between the source and the operating power supply terminal of the interface. A light source portion of an optical isolator is coupled to the receive data terminal, and a light activated switch portion of the optical isolator is coupled to the microcontroller.

Abstract: A power management mechanism for use in a computer system having a bus, a memory for storing data and instructions, and a central processing unit (CPU). The CPU runs an operating system having a power management virtual device driver (PMVxD) responsible for performing idle detection for devices. The PMVxD performs idle detection using event timers that provide an indicator as to the activity level. The PMVxD places idle local devices in a reduced power consumption state when no activity has occurred for a predetermined period of time.

Abstract: There is disclosed a power management signal generated from a computer for saving power of computer peripheral equipment by alternatively controlling a power supply or an operating state of the computer peripheral equipment, corresponding to a use state of a computer system, which the computer system has the computer peripheral equipment performing any one power management state among an on state, stand-by state, suspend state and off state.

Abstract: In a high speed digital computer data transfer system, a data bus driver, implemented using complementary metal-oxide-semiconductor (CMOS), reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Voltage overshoot and undershoot of the reduced bus logic levels are prevented by two "clamping diode" transistors. One of the two clamping diodes connected to the data bus is biased to a point just below conductivity, while the second clamping diode is biased to a point just below conductivity. As a result, if the output voltage rises above a selected level, the first clamping transistor acts as a conducting diode to pull the output voltage down, and, in a similar manner, if the output voltage at node falls below a selected level, then the second clamping transistor functions as a conducting diode to pull the output voltage up to an acceptable level.

Abstract: Communication, using a synchronous protocol, over a synchronous communications link, between synchronous application programs executed on a terminal (i.e., personal computer, PC) with an asynchronous byte-oriented interface and a PC with a synchronous frame orientated interface is made possible by enhancing the PC with the asynchronous byte-oriented interface with a device which modifies the data to be transmitted by inserting framing flags and transparency characters before the data passes through the COMM port (asynchronous byte-oriented interface) and extracting the transparency characters after the data exits the COMM port. As a consequence, the PC with the frame-oriented interface does not have to be modified.

Abstract: A plurality of priority determining units determine a bus use among a plurality of bus masters on the basis of bus request signals respectively from the bus masters and thereby generate bus grant signal. A bus request allocation unit allocates each bus request signals to one or more priority determining units on the basis of an allocation signal indicating which one or more priority determining units, among the plurality of priority determining units, to receive an allocation of the bus request signals from the plurality of bus masters. A control unit supplies the allocation signal to the bus request allocation unit and operates one or more priority determining units based on the allocation signal.

Abstract: Computer systems which emulate the operation of the Systempro and the Systempro registers, even though they are symmetric multiprocessors developed using the Intel P54C and P54CM or their equivalents. Further, the APICs in the systems are configured to emulate the interrupt handling of the Systempro. The FLUSH and CACHEON bits are emulated by flushing both processors and an external cache upon setting of the FLUSH bit or toggling of the CACHEON bit if the processors are the P54C and P54CM in a dual processor configuration. If the processors include separate level 2 caches, the CACHEON bit controls the enablement of the caches and the FLUSH bit causes a flushing of the caches for the respective processor. The SLEEP bit for the second processor is emulated by providing an initialization IPI to the second processor APIC without providing a startup IPI, and the RESET register bit is ignored.

Abstract: A configurable electronic work slate unit includes a customizable array of data devices and input/output devices which are selectively integrated in a compact and highly ergonomic structure. Increased operator productivity is accomplished by use of several possible user interface media including a multi-function display and input/output unit including a digitizer, position sensitive screen, and video display panel. Selectively integratable user interface components include a bar code scanner, RF modulator for radio frequency communication, modem, audio input/output, as well as the multi-purpose display. All components are integrated by use of a handle unit or module docking assembly which can house a battery as well as removable modules in a manner so as to minimize operator fatigue and discomfort, as well as enhance productivity.

Abstract: A data transmission circuit for a digital signal processor chip having a plurality of function blocks, a plurality of global buses which may be selectively connected to each other, and a plurality of local buses which may be selectively connected to an associated global bus and an associated function block. The circuit includes a plurality of first switches for selectively connecting the plurality of local buses to both the plurality of function blocks and the plurality of global buses, and a plurality of second switches means for selectively connecting the plurality of global buses. In a data transmission method for a digital signal processor chip, only those local buses and global buses necessary for data transmission are connected when data is transmitted between the plurality of function blocks. Therefore, movement of data through buses irrelevant to the desired operation is eliminated, and electrical consumption is reduced.

Abstract: A method and apparatus for producing an electronic circuit which allows a device to be connected to a bus, such as a system bus in a computer. The invention accepts user specified parameters for configuring a device adapter which interfaces the device to the bus, and thereafter generates a customized device adapter based on such user specified parameters. By using a common design macro, which is programmable, a user can easily specify and generate custom device adapters for a plurality of dissimilar devices to be connected to the bus. A resulting adapter architecture allows for multiple, dissimilar devices to interface to a computer bus with a single device adapter integrated circuit or card.

Abstract: An integrated device electronics (IDE) driver 40 operating in conjunction with a Basic Input/Output System (BIOS) driver (14), wherein both the IDE driver (40) and BIOS driver (14) are capable of powering down a hard disk drive (18). The IDE driver (40) monitors accesses to an alternate status register (32) by the BIOS driver (14). Upon detecting an access to the alternative status register (32), the IDE driver (40) commences writing any uncommitted data to the hard disk drive (18). The IDE driver (40) inhibits power down by the BIOS driver (14) until it finishes committing any uncommitted data to the hard disk drive (18). After all uncommitted data is committed to the hard disk drive (18), the BIOS driver (14) is permitted to power down the hard disk drive (18). A timer is set to reactivate the IDE driver (40). If the hard disk drive (18) was put to sleep, a reset from the BIOS driver (14) must occur before the IDE driver (40) can access the hard disk drive (18).

Abstract: A first-come-first-serve ("FCFS") scheduler that routes requests from two or more clients to a single resource. The FCFS scheduler contains a time stamp mechanism which provides a time stamp for each request. The scheduler provides resource access to the client with the oldest generated request and under a predetermined priority scheme in the event of simultaneous requests. The time stamps are generated by adders which add the current value of a time stamp counter with the number of client requests. The time stamp counter is incremented by the output of the adders. The updated value of the counter is decoded into a time stamp output value stored within time stamp registers. A hifind circuit reads the registers and generates an output signal associated with the set of registers, and corresponding client request, with the lowest time stamp. The output signal allows the client to access the resource.

Abstract: A control circuit is provided which enables the main CPU 23 to access a memory space of the sub CPU 1 by means of the test mode control register 4 which can be controlled via the main CPU bus 10. Also a control circuit is provided to branch into a break routine by comparing the value of the program counter 5 of the sub CPU 1 and the value set in the break vector register 7. Further, a control circuit which enables it to reset the sub CPU 1, to branch according to a test vector and to make break branch under the control of the main CPU 23 is provided, thereby making it easy to incorporate the sub CPU 1 on-chip in the conventional single CPU constitution. Thus testing environment and debugging environment for the sub CPU 1 is provided in the microcomputer having a plurality of CPUs on a single chip without connecting the exclusive test terminal of the sub CPU 1 or the sub CPU bus 28 with the outside.

Abstract: A busy targets table is created in a memory that can be either internal or external to a SCSI host adapter. Each entry in the table initially is set to a predetermined value. Prior to starting execution of each hardware request block, the host adapter performs a check to determine whether the hardware request block can be executed at this time by generating an offset into the busy targets table using a target address in the hardware request block. The host adapter then checks the entry in the busy targets table at the location of the offset. If the entry in the busy targets table at the location of the offset is the predetermined value, the device at the target address, i.e., the target, is available. Therefore, the execution of the hardware request block can proceed and so the host adapter overwrites the predetermined value at the offset in the table with a pointer to a storage location of said SCSI hardware request block and continues executing the hardware request block.

Abstract: A computer system is provided with a central processing unit (CPU), a bus master coupled to the CPU, and a plurality of interface cards that interface the computer system with peripheral devices. A plurality of host adapters are coupled between the bus master and the interface cards. The host adapters adapt signals between the CPU and the interface cards. Each host adapter generates a ready signal that when asserted indicates readiness of the host adapter to receive address information from the bus master and have data information read by the bus master. An address/data bus is coupled between the bus master and the host adapters. A single separate ready line is coupled between each of the host adapters and the bus master, each ready line carrying the ready signal from a different one of the host adapters to the bus master. The single ready signal carried by a single line serves both an address ready and a data ready signalling function, to thereby, reduce the pin count in the host adapter serving as a slave.

Abstract: A power management and packet delivery method for use in a wireless local area network (LAN) having a plurality of mobile battery powered user devices, the user devices in communication with each other, the power management and packet delivery technique for determining when a user device may transition from an active mode of operation to a sleep mode of operation and further for determining when a user device in the sleep mode of operation should transition to the active mode of operation. The method further operative to inform an intended destination device that data is forthcoming, thereby prohibiting that device from entering the sleep mode until after the data has been delivered.

Abstract: A data processing system operating under a multiprocessing hypervisor program subject to I/O interrupts during a polling interval of the hypervisor program includes one or more processors for executing the hypervisor program and host system and one or more guest systems under the hypervisor program, a storage system connected to the processor's by a bus for storing instructions, data and control information associated with the systems being executed by the processor, the storage system may be partitioned into a number of separate areas each associated with one of the concurrently operating systems, an input/output subsystem for generating I/O interrupts to the processors, apparatus for testing to determine if the system is operating in an interpretive execution mode, apparatus for determining whether a dedicated region facility is active, apparatus for testing whether an I/O enablement mask for a guest system has been set, apparatus for setting a flag if the guest system I/O enablement mask is set, apparatus

Abstract: In a data processor intended for fast partial clearing of a buffer memory which is based on a direct map scheme or a set associative scheme, a latch holds a comparison value used for partial clearing of the buffer memory, a comparator compares a tag read out of a tag array with the comparison value and asserts the clear signal in response to detection of the coincidence of both values, and a control logic circuit produces a hit signal and a new V flag from the old V flag, a coincidence signal, a clear signal and a type signal. In response to the detection of coincidence of values by the comparator, the V flag of a corresponding entry is shifted from the clear waiting state to the invalid state.