Abstract: A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request.

Abstract: A UART compatible to a prior art UART provides a baud rate generator which can accept a higher frequency crystal oscillator to generate baud rates compatible with baud rates generated by the prior art UART without increasing the size of the frequency division circuit. In one embodiment, the UART of the present invention provides the capability for programmable flow control, including flow control for binary file transfers, using user-programmable multiple-character flow control words. In one embodiment, a sleep mode allows power conservation in the UART of the present invention.

Abstract: A system having a virtual update capable read-only memory, includes a data storage system (270), and a device driver (272) which interfaces with the data storage system (270). The data storage system (270) includes a read-only memory device (274) which stores primary data, and an auxiliary memory device (276) which stores supplementary data reflecting updates to the primary data. The device driver (272) has a read handler which provides a response to a read request consisting of a combination of primary data from the read-only memory device (274) and supplementary data from the auxiliary memory device (276).

Abstract: A computer bus bridge interconnects first and second buses, the first bus being big-endian and the second bus being little-endian. First address and size signals received from the first bus during a first bus cycle are converted into second address and data unit enable signals for transmission on the second bus during a second bus cycle. The first address comprises a low-order address portion and a remaining upper-order address portion. The data unit enable signals are generated from the low-order address portion and the size signals of the first bus. An address offset is generated from the data unit enable signals. The remaining upper-order address portion of the first address are then concatenated with the address offset and a predetermined lower address portion for use as the second address. The data unit enable signals may designate, say, up to 4 possible data bytes being transferred during a single beat on the second bus.

Abstract: An interrupt mechanism within a data processing system where every expected interrupt has a unique interrupt signature. This interrupt signature is known by the system interrupt handler of the interrupt's particular type, such as external, timer, divide by zero, etc. For example, external interrupt is one type of interrupt, and the FLIH of external interrupt must know the signatures of all expected external interrupts. Every expected interrupt has its signature stored in a plurality of processor general purpose registers. The name of these registers must be known by the interrupt handler that will handle the interrupt. The interrupt handler preserves the processor state when it tries to verify signatures. If a signature match is found, the interrupt handler will branch to the corresponding second level interrupt handler for normal interrupt processing. If the second level interrupt handler is shared by some sources, then the second level interrupt handler must query these sources for the ownership.

Abstract: A superscalar complex instruction set computer ("CISC") processor (100) having a reduced instruction set computer ("RISC") superscalar core (110) includes an instruction cache (104) which identifies and marks raw x86 instruction start and end points and encodes "pre-decode" information, a byte queue (106) which is a queue of aligned instruction and pre-decode information of the "predicted executed" state, and an instruction decoder (108) which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue. The instruction decoder includes in each dispatch position a logic-based conversion path, a memory-based conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer (400) directs x86 instructions from the byte queue to the conversion paths.

Abstract: A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.

Abstract: A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code.

Abstract: A model of a finite state machine suited for implementation in a microcomputer includes logical specifications stored in memory which determine whether a change of outputs should be effected in response to predetermined combinations of input parameters and whether a change of state should be effected based on stored logical conditions of input parameters. Additional control of the flow of the steps of the finite state machine are under the control of the designer wherein a designer controlled variable permits a selection following a state transition as to whether or not an immediate test or input parameters will be made to determine whether additional actions are required or whether a return to a determination of state transition is to be made.

Abstract: A system for determining the connections between a PCMCIA controller and a programmable interrupt controller (PIC) by simulating an interrupt request from the PCMCIA controller and then evaluating the values contained in the interrupt request register of the PIC. An interrupt request association record is stored in response to receiving the simulated interrupt request at one of the interrupt request register inputs of the programmable interrupt controller. The interrupt request association record assigns the selected interrupt request line to the interrupt request register input that received the interrupt request signal. An interrupt request output from the PCMCIA controller is considered to be connected to a particular interrupt request register input of the PIC if a value in the interrupt request register of the PIC transitions from a logic low state to a logic high state, and then returns to the logic low state.

Abstract: Apparatus and a method by which the flow of commands to an input/output device may be halted when the device is unable to respond to a command decoded to its address space. The apparatus includes circuitry for ascertaining whether the input/output device is able to respond to a command decoded by the decoding circuit, a circuit for storing the data and address of a command transferred to the input/output device to which the input/output device is unable to respond, and circuitry for generating a signal to disable immediately the flow of commands to the input/output device and an interrupt to assure that the unimplemented command is handled in an expeditious manner.

Abstract: A programmable controller apparatus, and a method for operating a programmable controller apparatus, which does not require a sequence program to initialize the device memory at the start of operation of the programmable controller apparatus. Further, the apparatus and method both allow the contents of the device memory of the programmable controller to be changed at a specified time, during a simulation operation, or when data at a predetermined address of the device memory represents a predetermined value. The programmable controller operates based on the contents of the device memory, and comprises a second memory for sequentially storing data including address data indicating a first address of the device memory and write data to be written to a predetermined number of addresses of the device memory beginning at the first address, and a memory changing device for changing the contents of the device memory in accordance with the data stored in the second memory.

Abstract: Power is conserved in a video subsystem by inactivating a pixel clock (PCLK) and reducing frequency of a memory clock (MCLK) responsive to an indication of user inactivity. The inactivation of PCLK reduces the power consumed in the RAMDAC, frame buffer, phase lock loop (PLL) clock circuit, and to a smaller extent, the video controller. Reducing the frequency of MCLK conserves power in the video controller and the PLL, while maintaining the integrity of the data in the frame buffer. Significant power savings can be accomplished with minimal BIOS or video controller programming and minimal transfer of state information prior to power-down.

Abstract: A removable CPU module for use in a data processing system. The CPU module includes at least one CPU having a first data width, and a first data bus of the same data width coupled to the CPU. A connector is coupled to the first data bus for connecting to a circuit board having a second data bus. The second data bus has a second data width which is different from the first data width. The CPU module is configured such that it is compatible with the second data bus. In one embodiment, the removable CPU module includes a third data bus coupled to the first data bus and the connector, which is a duplicate of and connected in parallel with the first data bus. The third data bus facilitates compatibility between the CPU module and the second data bus.

Abstract: A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

Abstract: A semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said data in said first format using said stored address in said first memory device. The component also comprises a translator device coupled to said second memory device capable of transmitting said address of said data in said second format corresponding to said address of said data in said first format, wherein the second format contains the same amount of information as the first format.

Abstract: A multiple processor type computing system and an associated method of manufacturing the same from first and second computer systems, each of which include a PCI bus and both a processor and LAN device coupled to the PCI bus, which are selected such that the processors of the computer systems are configured to execute software utilizing different operating systems. Each LAN device is installed on the PCI bus using a PCI interface and is comprised of a data register, a data FIFO and a LAN controller coupled together using internal circuity. Also coupled to the internal circuitry is a serial I/O port used to connect the LAN device to a network. From these, a multiple processor computing system is manufactured by removing the serial I/O port from each of the LAN devices to expose the internal circuitry thereof.

Abstract: An interface device (102) and corresponding method for coupling a peripheral controller (117) to a host computer (100), the interface device including an emulated universal asynchronous receiver transmitter (UART) (113) for the host computer. The interface device further includes a plurality of registers (203), preferably a control (215), status (227), and data register, such as a multi-register data buffer (401), corresponding to the registers of a UART, a host computer port (112), preferably compatible with a PCMCIA standard, that includes an address map for the plurality of registers (203), a peripheral controller port (114) providing an address mapped parallel interface to the plurality of registers (203), and control logic (207) for providing status signals, including UART status signals, to the host computer port and to the peripheral controller port.

Abstract: A personal computer system utilizes a simplified motherboard having connectors on the motherboard that are electrically connected to data, address, control, power and ground signals necessary for expansion and upgrade of the computer system and a riser card or cards having the desired interface connectors and logic circuits thereon. The present invention provides for operatively and removably coupling a plurality of I/O expansion cards, host local bus interfaces and future system upgrades for the computer system without burdening the base cost thereof. The computer system may be expanded or upgraded at any time during manufacture or in the field. A simple and low cost common motherboard is utilized in the manufacture of the computer systems, resulting in lower manufacturing costs. A base computer system may be easily upgraded when more features are desired.

Abstract: A system for power management within a microprocessor by selectively interrupting clock drivers to a Translation Lookaside Buffer (TLB) unit. The present invention interrupts the clock supply to the TLB unit when the TLB unit is disabled by the microprocessor and during periods of time when it is not anticipated that the TLB unit will be accessed. The present invention monitors a page disable bit to indicate when paging is not required within the microprocessor. Further, the present invention monitors instructions within an instruction queue to determine which may utilize the TLB unit for address translation operations. By interrupting the clock supply, the TLB unit (composed of BiCMOS or CMOS circuits) will not consume power when the unit is not needed. The present invention also includes a mechanism for detecting when the TLB unit is to be used and for powering up the unit. The present invention also includes circuitry for preventing the TLB unit from powering down when the TLB unit is busy.