Abstract: A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.

Abstract: An intelligent bus bridge contained in a single integrated circuit chip is disclosed along with computer systems and server systems that employ intelligent input/output subsystems. The intelligent bus bridge includes a local processor coupled for communication over a local component bus, a local memory controller that enables access to a local memory from the local component bus, and a component bus bridge that propagates accesses between the local component bus and a system component bus. The single integrated circuit chip enables dual-porting of the local memory controller without significant increases in input/output pins. A mode control input to the intelligent bus bridge indicates whether the intelligent bus bridge functions in a local master mode or a host master mode in a computer or server system.

Abstract: A programmable arbiter providing for dynamic configuration of prioritization schemes is implemented using a simple, but effective structure. One or more arbiter banks are structured in a cascading manner. Each arbiter bank receives a predetermined number of the set of bus requests to be arbitrated. Each bank is separately programmed to provide a rotating or fixed priority scheme to evaluate the priority of the bus requests. Thus by separately programming the arbiter banks to operate in a fixed priority or rotating priority manner, a flexible, programmable arbiter is created which can operate according to a fixed, rotating or hybrid priority scheme and is adaptable to a variety of applications.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: An interconnect topology providing enhanced fault tolerance to a multi-component data processing system. The topology utilizes a plurality of rings for interconnecting multiple system components, or cards, at least two of which are indirectly connected so that communication therebetween is through a third component. Each of the system components is coupled to a set of at least two different rings and includes interface circuits for routing data and a bridge for permitting data to be transferred between the at least two rings.

Abstract: A bridge interface for a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer, and a scatter/gather unit coupled between the ISA bus and the DMA control circuit. The scatter/gather unit selectively provides the programming signals to the DMA control circuit directly or causes the programming signals to be provided over the ISA bus. Providing the programming signals to the DMA control circuit directly from the programming controller of the scatter/gather unit takes advantage of the location of both the DMA control circuit and the scatter/gather unit on the bridge chip.

Abstract: A method of managing an interface to an internal message pipe, such as an FDDI bus, comprises sending a status enquiry message to request the status of each PVC having a DLCI in a specified range, receiving a subset status message containing sequence exchange numbers corresponding to the last status message sent out, updating the contents of a station's PVC's in response to the received subset status message, and propagating PVC status changes between entities on the pipe.

Abstract: An apparatus that connects to a standard PCMCIA interface of a microprocessor-based computer which typically communicates with only a single external device through the interface enables the computer to communicate with multiple external devices through the one PCMCIA interface. The apparatus operates to implement a method which transfers data from multiple devices to a personal computer through a single PCMCIA interface.

Abstract: Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD.

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks.

Abstract: A method and apparatus for placing a microprocessor in and out of a reduced power consumption state utilizing system interrupts in a computer system. The method of the present invention intercepts instructions being executed by the processor before placing the processor in a reduced power consumption state. On a request for the processor to exit the reduced power consumption state, the method of the present inventions allows the processor to execute pre-determined resume instructions to wait out any voltage level fluctuations in the processor as it exits the reduced power consumption state, before allowing the processor to continue execution of the instructions intercepted prior to placing the processor in the reduced power consumption state.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue.

Abstract: An SCSI controller having a mechanism for receiving a power down request indicating that the SCSI disk drives should be spun down. Preferably, the SCSI controller has an input for receiving a power down request signal. The SCSI controller monitors activity on the SCSI bus and asserts a signal indicative thereof to power management logic. The power management logic monitors the resources of the computer system and generates a system interrupt and the power down signal to initiate a power down mode when the computer system is determined to be idle. The CPU receives the system interrupt to perform traditional power down sequences. The SCSI controller receives the power down signal and generates a SCSI interrupt. The CPU also receives the SCSI interrupt and executes an SCSI device driver. The SCSI device driver determines that power down mode is being initiated, and sends spin down request commands to the SCSI controller for each SCSI drive. The SCSI controller powers down each of the SCSI devices in response.

Abstract: A method and a switching system for connecting multiple requestors to multiple memory units simultaneously. This is accomplished by a switching system that employs multiplexing logic, control logic, multiple data input and output ports and a unique system interconnection topology. Independent data input ports comprised of multiplexing logic controlled by a control logic, simultaneously channel multiple fetch and store commands from the requestors to the memory units. Similarly, independent data output ports comprised of a second multiplexing logic controlled by a second control logic, simultaneously channels multiple return signals from the memory units to the requestors. The switching system of the present invention incorporates the unique system interconnection topology concept of feed-through boards and modular backplane boards.

Abstract: Method and apparatus for using a field-programmable gate-array circuit as a crossbar switch. In order to connect a first port of the crossbar switch to a second port, an address within the field-programmable gate-array circuit is calculated, and a first data pattern to load at that address is determined. A second data pattern to load at that address is determined in order to disconnect the first port from the second port. The first port is then connected to the second port by loading the first data pattern at the calculated address in the field-programmable gate-array circuit. Subsequently the first port is disconnected from the second port by loading the second data pattern at the calculated address in the field-programmable gate-array circuit. Mechanisms are provided for analog or digital ports, for multiple-bit digital ports, for combinations of logical functions with the crossbar-switch functions, and for latching the data within the crossbar switch.

Abstract: Shadow registers for processing interruption are provided in a CPU. When the control shifts to interruption routine, the shadow registers are used for the interruption routine by changing the use of ordinary registers thereto, and the ordinary registers are prohibited to be used during a period of the interruption. Subsequently to the finish of the interruption, the ordinary registers are re-used without the necessity of the store and the re-store of the ordinary registers.

Abstract: Modular expansion of a backplane is achieved by means of a modular backplane circuit board that plugs into the backplane side of a backplane parallel to that backplane. The backplane board provides a parallel backplane path between boards on the computer system. When unit boards are added to the foreplane side which require additional electrical paths for connection purposes, a modular backplane board may be added to the backplane side of the backplane to provide such path. In the preferred embodiment a gate array is added to the backplane board to provide management functions in handling the electrical connections on the backplane board.

Abstract: Power is conserved in a video subsystem by inactivating a pixel clock (PCLK) and reducing frequency of a memory clock (MCLK) responsive to an indication of user inactivity. The inactivation of PCLK reduces the power consumed in the RAMDAC, frame buffer, phase lock loop (PLL) clock circuit, and to a smaller extent, the video controller. Reducing the frequency of MCLK conserves power in the video controller and the PLL, In order to maintain the integrity of the data in the frame buffer, the refresh rate programmed by the video controller is increased to offset the reduction of the MCLK frequency. Significant power savings can be accomplished with minimal BIOS or video controller programming and minimal transfer of state information prior to power-down.

Abstract: A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle.

Abstract: A personal computer system utilizes a simplified motherboard having connectors on the motherboard that are electrically connected to data, address, control, power and ground signals necessary for expansion and upgrade of the computer system and a riser card or cards having the desired interface connectors and logic circuits thereon. The present invention provides for operatively and removably coupling a plurality of I/O expansion cards, host local bus interfaces and future system upgrades for the computer system without burdening the base cost thereof. The computer system may be expanded or upgraded at any time during manufacture or in the field. A simple and low cost common motherboard is utilized in the manufacture of the computer systems, resulting in lower manufacturing costs. A base computer system may be easily upgraded when more features are desired.